P10C68/P11C68
PRELIMINARY INFORMATION
DS3600-1.2 September 1992
P10C68/P11C68
(Previously PNC10C68 and PNC11C68
)
CMOS/SNOS NVSRAM
HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
(Supersedes DS3159-1.3, DS3160-1.3, DS3234-1.1, DS3235-1.1)
The P10C68 and P11C68 are fast static RAMs (35 and 45
ns) with a non-volatile electically-erasable PROM (EEPROM)
cell incorporating in each static memory cell. The SRAM can
be read and written an unlimited number of times while
independent non-volatile data resides in PROM.
On the P10C68 data may easily be transferred from the
SRAM to the EEPROM (STORE) and from the EEPROM back
to the SRAM ( RECALL) using the NE (bar) pin. The Store and
Recall cycles are initiated through software sequences on the
P11C68. These devices combine the high performance and
ease of use of a fast SRAM with the data integrity of non-
volatility.
The P10C68 and P11C68 feature the industry standard
pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and
ceramic dual-in-line packages.
NE
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
ss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
FEATURES
I
Non-Volatile Data Integrity
I
10 year Data Retention in EEPROM
I
35ns and 45ns Address and Chip Enable Access Times
I
20ns and 25ns Output Enable Access
I
Unlimited Read and Write to SRAM
I
Unlimited Recall Cycles from EEPROM
I
10
4
Store Cycles to EEPROM
I
Automatic Recall on Power up
I
Automatic Store Timing
I
Hardware Store Protection
I
Single 5V
±
10% Operation
I
Available in Standard Package 28-pin 0.3-inch DIL
plastic and ceramic
I
Commercial and Industrial temperature ranges
ORDERING INFORMATION
(See back page)
Figure 1. Pin connections - top view.
Pin Name
A
0
- A
12
W
DQ
0
- DQ
7
E
G
V
CC
V
SS
Pin 1
NE
Pin 1 N/C
Function
Address inputs
Write enable
Data in/out
Chip enable
Output enable
Power (+5V)
Ground
Non volatile enable P10C68
No connection
P11C68
1
P10C68/P11C68
EEPROM ARRAY
256 x 256
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
12
R
O
W
D
E
C
O
D
E
R
STATIC RAM
ARRAY
256 x 256
STORE
RECALL
STORE/
RECALL
CONTROL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
I
N
P
U
T
B
U
F
F
E
R
S
COLUMN I/O
COLUMN DECODER
A
0
A
1
A
2
A
10
A
11
G
NE (P10C68 only)
E
W
F
igure 2. Logic block diagram.
2
P10C68/P11C68
ABSOLUTE MAXIMUM RATINGS
Voltage on typical input
relative to VSS
Voltage on DQ0-7 and G(bar)
Temperature under Bias
Storage temperature
Power dissipation
DC output current
-0.6V to 7.0V
-0.5V to (Vcc + 0.5V)
-55°C to + 125°C
-65°C to + 150°C
1W
15mA
NOTE
Stresses greater than those listed in the Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation of
the device at any other conditions than those indicated in the
operational sections of the specification is not implied.
Exposure to absolute maximum ratings conditions for
extended periods may affect reliability.
(one output at a time, one second duration)
DC OPERATING CONDITIONS
Parameter
Symbol
Min.
Supply voltage
Input logic '1' voltage
Input logic '0' voltage
Ambient operating temperature
commercial
industrial
V
CC
V
IH
V
IL
T
amb
T
amb
Value
Typ.
5.0
2.2
V
SS
-0.5
0
-40
V
CC
+0.5
0.8
+70
+85
Max.
V
V
V
o
o
Units
Conditions
All inputs
All inputs
C
C
DC ELECTRICAL CHARACTERISTICS
Commercial temperature range
Test conditions (unless otherwise stated):
Tamb = 0°C to 70°C, Vcc = +5V (See notes 1, 2 and 3)
Characteristic
Symbol
Min.
Average power supply
current
Average power supply current
during STORE cycle
Average power supply current
(standby, cycling TTL input levels)
I
CC1
I
CC2
I
SB1
Value
Max.
75
65
50
mA
mA
mA
t
AVAV
= 35ns
t
AVAV
= 45ns
All inputs at V
IN
≤
0.2V
t
AVAV
= 35ns
t
AVAV
= 45ns
E(bar)
≥V
IH
, all other inputs
cycling
E (bar)≥(V
CC
-0.2V), all other
inputs at V
IN
≤0.2V
or
≥(V
CC
-
0.2V)
V
CC
= max, V
IN
= V
SS
to V
CC
V
CC
= max, V
IN
= V
SS
to V
CC
I
OUT
= 4mA
I
OUT
= 8mA
Units
Conditions
23
20
mA
mA
Average power supply current
(standby, stable CMOS input levels)
I
SB2
1
mA
Input leakage current (any input)
Off state output leakage current
Output logic '1' voltage
Output voltage '0' voltage
I
ILK
I
OLK
V
OH
V
OL
±1
±5
2.4
0.4
µA
µA
V
V
NOTES
1.
I
CC1
is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
2.
Bringing E (bar)
≥
V
IH
will not produce standby currents levels until any non-volatile cycle in progress has timed out. See
Mode Selection table.
3.
I
CC2
is the average current required for the duration of the STORE cycle (t
STORE
) after the sequence that initiates the
cycle.
3
P10C68/P11C68
Industrial temperature range
Test conditions (unless otherwise stated):
Tamb = -40˚C to 70˚C, Vcc = +5V
±
10% (See notes 4, 5 and 6)
Characteristic
Symbol
Min.
Average power supply
current
Average power supply current
during STORE cycle
Average power supply current
(standby, cycling TTL input levels)
I
CC1
I
CC2
I
SB1
Value
Max.
80
75
50
mA
mA
mA
t
AVAV
= 35ns
t
AVAV
= 45ns
All inputs at V
IN
≤
0.2V
t
AVAV
= 35ns
t
AVAV
= 45ns
E(bar)
≥V
IH
, all other inputs
cycling
E (bar)≥(V
CC
-0.2V), all other
inputs at V
IN
≤0.2V
or
≥(V
CC
-
0.2V)
V
CC
= max, V
IN
= V
SS
to V
CC
V
CC
= max, V
IN
= V
SS
to V
CC
I
OUT
= 4mA
I
OUT
= 8mA
Units
Conditions
27
23
mA
mA
Average power supply current
(standby, stable CMOS input levels)
I
SB2
1
mA
Input leakage current (any input)
Off state output leakage current
Output logic '1' voltage
Output voltage '0' voltage
I
ILK
I
OLK
V
OH
V
OL
±1
±5
2.4
0.4
µA
µA
V
V
NOTES
4.
I
CC1
is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
5.
Bringing E (bar)
≥
V
IH
will not produce standby currents levels until any non-volatile cycle in progress has timed out. See
Mode Selection table.
6.
I
CC2
is the average current required for the duration of the STORE cycle (t
STORE
) after the sequence that initiates the
cycle.
AC TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load
V
SS
to 3V
≤5ns
1.5V
See Figure 3
5.0V
480 Ohms
CAPACITANCE
T
amb
= 25°C, f = 1.0MHz (see note 7)
Parameter
Input capacitance
Output capacitance
Symbol
C
IN
C
OUT
Max. Units
5
7
pF
pF
Conditions
∆V=0
to 3V
∆V=0
to 3V
OUTPUT
255
Ohms
30p
INCLUDING
SCOPE AND
FIXTURE
NOTE
7. These parameters are characterised but not 100% tested.
Figure 3. AC output loading.
4
P10C68/P11C68
SRAM MEMORY OPERATION
Test conditions (unless otherwise stated):
Commercial and Industrial Temperature Range
Tamb = -40°C to + 85°C, Vcc = + 5V
±
10%
READ CYCLES 1 AND 2
(See note 8)
Symbol
Standard
t
ELQV
t
AVAV
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
t
ELICCH
t
EHICCL
t
WHQV
Alternative
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
OHZ
t
OLZ
t
HZ
t
PA
t
PS
t
WR
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Outout disable to output inactive
Chip enable to power active
Chip disable to power standby
Write recovery time
P10C68-35
P11C68-35
Min.
Max.
35
35
35
20
5
5
20
0
15
0
25
45
0
25
55
0
20
5
5
25
45
45
25
P10C68-45
P11C68-45
Max.
Min.
45
Parameter
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
10
11
11
12
12
NOTES
8.
E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion. NE (bar) must be
≥
VIH during entire cycle.
9.
For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle.
10.
Device is continuously selected with E (bar) low, and G (bar) low.
11.
Measured
±200mV
from steady state output voltage. Load capacitance is 5pF.
12.
Parameter guaranteed but not tested.
t
AVAV
ADDRESS
t
AVQV
t
AXQX
DQ (DATA OUT)
DATA VALID
W
t
WHQV
Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10).
5
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