Freescale Semiconductor
Technical Data
MPC7448EC
Rev. 1, 11/2005
MPC7448
RISC Microprocessor
Hardware Specifications
This document is primarily concerned with the PowerPC™
MPC7448. The MPC7448 is an implementation of the
PowerPC microprocessor family of reduced instruction set
computer (RISC) microprocessors. This document describes
pertinent electrical and physical characteristics of the
MPC7448. For information regarding specific MPC7448
part numbers covered by this document and part numbers
covered by other documents, refer to
Section 11, “Part
Numbering and Marking.”
For functional characteristics of
the processor, refer to the
MPC7450 RISC Microprocessor
Family Reference Manual.
To locate any published updates for this document, refer to
the website listed on the back cover of this document.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Comparison with the MPC7447A, MPC7447,
MPC7445, and MPC7441 . . . . . . . . . . . . . . . . . . . . . . .7
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical and Thermal Characteristics . . . . . . . . . . . . .9
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . .29
System Design Information . . . . . . . . . . . . . . . . . . . . .35
Document Revision History. . . . . . . . . . . . . . . . . . . . .56
Part Numbering and Marking . . . . . . . . . . . . . . . . . . .57
1
Overview
The MPC7448 is the sixth implementation of fourth-
generation (G4) microprocessors from Freescale. The
MPC7448 implements the full PowerPC 32-bit architecture
and is targeted at networking and computing systems
applications. The MPC7448 consists of a processor core and
a 1-Mbyte L2.
Figure 1
shows a block diagram of the MPC7448. The core
is a high-performance superscalar design supporting a
double-precision floating-point unit and a SIMD multimedia
unit. The memory storage subsystem supports the MPX bus
protocol and a subset of the 60x bus protocol to main
memory and other system resources.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
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Instruction Unit
Branch Processing Unit
Fetcher
Tags
IBAT Array
BHT (2048-Entry)
Dispatch
Unit
Data MMU
SRs
(Original)
VR Issue
(4-Entry/2-Issue)
DBAT Array
GPR Issue
(6-Entry/3-Issue)
FPR Issue
(2-Entry/1-Issue)
128-Entry
DTLB
Tags
LR
BTIC (128-Entry)
CTR
Instruction Queue
(12-Word)
SRs
(Shadow)
128-Entry
ITLB
Instruction MMU
128-Bit (4 Instructions)
32-Kbyte
I Cache
32-Kbyte
D Cache
Reservation
Stations (2-Entry)
EA
Load/Store Unit
Vector Touch Engine
+ (EA Calculation)
Finished
Stores
L1 Castout
PA
FPR File
16 Rename
Buffers
Reservation
Stations (2)
Completes up
to three
instructions
per clock
VR File
16 Rename
Buffers
Integer
Unit 2
Integer
Integer
Integer
Unit 122
Unit
Unit
(3)
+++
32-Bit
32-Bit
x÷
Vector
FPU
32-Bit
128-Bit
128-Bit
16 Rename
Buffers
Reservation
Stations (2)
GPR File
Reservation
Reservation
Reservation
Station
Station
Station
Vector
Touch
Queue
Floating-
Point Unit
L1 Push
Completed
Stores
+ x÷
FPSCR
Load Miss
64-Bit
64-Bit
Vector
Integer
Unit 1
1-Mbyte Unified L2 Cache Controller
System Bus Interface
Block 1 (32-Byte)
Status
Load
Queue (11)
Overview
Additional Features
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
• Out-of-Order Issue of AltiVec Instr.
Completion Unit
96-Bit (3 Instructions)
Completion Queue
(16-Entry)
Reservation Reservation Reservation Reservation
Station
Station
Station
Station
Figure 1. MPC7448 Block Diagram
L1 Service
Queues
Line
Block 0 (32-Byte)
Tags Status
L1 Castouts
(4)
L2 Store Queue (L2SQ)
Snoop Push/
Interventions
Vector
Permute
Unit
Vector
Integer
Unit 2
Memory Subsystem
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1
L1 Store Queue
(LSQ)
L1 Load Queue (LLQ)
L1 Load Miss (5)
Bus Store Queue
Castout
Queue (5) /
Push
Queue (6)
1
Bus Accumulator
L2 Prefetch (3)
Instruction Fetch (2)
Cacheable Store Miss (2)
36-Bit
Address Bus
64-Bit
Data Bus
Freescale Semiconductor
Notes:
The Castout Queue and Push Queue share resources such for a combined total of 6 entries.
The Castout Queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.
Features
2
Features
This section summarizes features of the MPC7448 implementation of the PowerPC architecture.
Major features of the MPC7448 are as follows:
• High-performance, superscalar microprocessor
— Up to four instructions can be fetched from the instruction cache at a time.
— Up to three instructions plus a branch instruction can be dispatched to the issue queues at a
time.
— Up to 12 instructions can be in the instruction queue (IQ).
— Up to 16 instructions can be at some stage of execution simultaneously.
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
• Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
of branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
be made available from the instruction cache. Typically, a fetch that hits the BTIC provides
the first four instructions in the target stream.
– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of
prediction—not taken, strongly not taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register (bclr) instructions
— Four integer units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions.
– IU2 executes miscellaneous instructions, including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions.
— Five-stage FPU and 32-entry FPR file
– Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1
Freescale Semiconductor
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Features
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add
instructions (for example,
vaddsbs, vaddshs,
and
vaddsws).
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector
multiply add instructions (for example,
vmhaddshs, vmhraddshs,
and
vmladduhm).
– Vector floating-point unit (VFPU)
•
•
•
•
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
– Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle
throughput
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– A dedicated adder calculates effective addresses (EAs).
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.
— A maximum of three instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to dispatch (this includes instructions that
are assigned a space in the CQ but not in an issue queue).
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— Retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of
it have been completed, the instruction has finished executing, and no exceptions are pending
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Features
•
•
•
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache
— No snooping of instruction cache except for
icbi
instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
— On-chip, 1-Mbyte, eight-way set-associative unified instruction and data cache
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Parity support on cache tags
— ECC or parity support on data
— Error injection allows testing of error recovery software
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address, 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set-associative and use an LRU replacement algorithm.
– TLBs are hardware- or software-reloadable (that is, a page table search is performed in
hardware or by system software on a TLB miss).
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1
Freescale Semiconductor
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