24AA16
16K 1.8V I
2
C
™
Serial EEPROM
FEATURES
• Single supply with operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 3
µ
A standby current typical at 1.8V
• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I
2
C
™
compatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 4,000V
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature ranges
- Commercial (C):
0˚C to +70
°
C
- Industrial (I):
-40
°
C to +85
°
C
PACKAGE TYPES
PDIP
A0
A1
A2
V
SS
1
2
3
4
24AA16
8
7
6
5
V
CC
WP
SCL
SDA
8-lead
SOIC
A0
A1
A2
1
2
3
4
24AA16
8
7
6
5
V
CC
WP
SCL
SDA
V
SS
14-lead SOIC
NC
A0
A1
NC
A2
V
SS
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
V
CC
WP
NC
SCL
SDA
NC
24AA16
DESCRIPTION
The Microchip Technology Inc. 24AA16 is a 1.8 volt 16K
bit Electrically Erasable PROM. The device is orga-
nized as eight blocks of 256 x 8-bit memory with a 2-
wire serial interface. Low voltage design permits oper-
ation down to 1.8 volts with standby and active currents
of only 3
µ
A and 1 mA, respectively. The 24AA16 also
has a page-write capability for up to 16 bytes of data.
The 24AA16 is available in the standard 8-pin DIP and
both 8-lead and 14-lead surface mount SOIC pack-
ages.
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA
SCL
YDEC
V
CC
V
SS
I
2
C is a trademark of Philips Corporation.
SENSE AMP
R/W CONTROL
©
1996 Microchip Technology Inc.
DS21054E-page 1
This document was created with FrameMaker 4 0 4
24AA16
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
V
SS
SDA
SCL
WP
V
CC
A0, A1, A2
PIN FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+1.8V to 5.5V Power Supply
No Internal Connection
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS .................
-0.6V to V
CC
+1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins
..................................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= 1.8V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Parameter
Symbol
Min
Typ
Max
Units
V
V
V
V
µ
A
µ
A
pF
mA
mA
mA
mA
µ
A
µ
A
µ
A
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
Low level input voltage
V
IL
—
.3 V
CC
Hysteresis of Schmitt trigger inputs
V
HYS
.05 V
CC
—
Low level output voltage
V
OL
—
.40
-10
10
Input leakage current
I
LI
Output leakage current
I
LO
-10
10
Pin capacitance
C
IN
,
—
10
(all inputs/outputs
C
OUT
3
—
Operating current
I
CC
Write
—
—
0.5
—
1
—
—
I
CC
Read
—
0.05
—
Standby current
I
CCS
—
—
100
—
—
30
—
3
—
Note: This parameter is periodically sampled and not 100% tested.
(Note)
I
OL
= 3.0 mA, V
CC
= 1.8V
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 1.8V, SCL = 100 kHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 1.8V, SCL = 100 kHz
V
CC
= 5.5V, SDA=SCL=V
CC
V
CC
= 3.0V, SDA=SCL=V
CC
V
CC
= 1.8V, SDA=SCL=V
CC
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
T
HD
:
STA
T
SU
:
STO
SDA
START
STOP
DS21054E-page 2
©
1996 Microchip Technology Inc.
24AA16
TABLE 1-3:
AC CHARACTERISTICS
STANDARD
MODE
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold
time
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
V
CC
= 4.5-5.5V
FAST MODE
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Max
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
100 pF
(Note 3)
Parameter
Symbol
Units
Remarks
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Output fall time from V
IH
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WR
—
—
—
—
10M
250
50
10
—
20 +0.1
C
B
—
—
10M
250
50
10
—
ns
ns
ms
Byte or Page mode
cycles 25
°
C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions
3: The combined T
SP
and V
HYS
=specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
HD
:
DAT
T
SP
T
AA
T
SU
:
DAT
T
SU
:
STO
T
AA
SDA
OUT
T
HD
:
STA
T
BUF
©
1996 Microchip Technology Inc.
DS21054E-page 3
24AA16
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24AA16 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24AA16 works
as slave. Both, master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24AA16 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
SCL
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21054E-page 4
©
1996 Microchip Technology Inc.
24AA16
3.6
Device Addressing
4.0
4.1
WRITE OPERATION
Byte Write
A control byte is the first byte received following the start
condition from the master device. The control byte con-
sists of a 4-bit control code, for the 24AA16 this is set as
1010 binary for read and write operations. The next three
bits of the control byte are the block select bits (B2, B1,
B0). They are used by the master device to select which
of the eight 256 word blocks of memory are to be
accessed. These bits are in effect the three most signifi-
cant bits of the word address. It should be noted that the
protocol limits the size of the memory to eight blocks of
256 words, therefore the protocol can support only one
24AA16 per system.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24AA16 monitors the
SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24AA16 will select a read
or write operation.
Operation
Read
Write
Control
Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24AA16. After receiving
another acknowledge signal from the 24AA16 the mas-
ter device will transmit the data word to be written into
the addressed memory location. The 24AA16 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24AA16 will not generate acknowledge
signals (Figure 4-1).
4.2
Page Write
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
B2
B1
B0
The write control byte, word address and the first data
byte are transmitted to the 24AA16 in the same way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to sixteen data bytes to the
24AA16 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
X = Don’t care
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
SDA LINE
S
A
C
K
A
C
K
A
C
K
P
BUS ACTIVITY
FIGURE 4-2:
BUS ACTIVITY
MASTER
PAGE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
S
T
O
P
DATA n
DATA n + 1
DATA n + 15
SDA LINE
BUS ACTIVITY
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P
©
1996 Microchip Technology Inc.
DS21054E-page 5
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