M
FEATURES
24C02C
2K 5.0V I
2
C
™
Serial EEPROM
PACKAGE TYPES
PDIP/SOIC
A0
A1
A2
Vss
1
8
Vcc
WP
SCL
SDA
• Single supply with operation from 4.5 to 5.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
• Organized as a single block of 256 bytes (256 x 8)
• Hardware write protection for upper half of array
• 2-wire serial interface bus, I
2
C compatible
• 100 kHz and 400 kHz compatibility
• Page-write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• Fast 1 mS write cycle time for byte or page mode
• Address lines allow up to eight devices on bus
• 1,000,000 erase/write cycles guaranteed
• ESD protection > 4,000V
• Data retention > 200 years
• 8-pin PDIP, SOIC or TSSOP packages
• Available for extended temperature ranges
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I):
-40
°
C to +85
°
C
- Automotive (E):
-40
°
C to +125
°
C
24C02C
2
3
4
7
6
5
TSSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24C02C
DESCRIPTION
The Microchip Technology Inc. 24C02C is a 2K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial inter-
face. Low current design permits operation with typical
standby and active currents of only 10
µ
A and 1 mA
respectively. The device has a page-write capability for
up to 16 bytes of data and has fast write cycle times of
only 1 mS for both byte and page writes. Functional
address lines allow the connection of up to eight
24C02C devices on the same bus for up to 16K bits of
contiguous EEPROM memory. The device is available
in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and
TSSOP packages.
BLOCK DIAGRAM
A0 A1 A2
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
SDA SCL
Vcc
Vss
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
I
2
C is a trademark of Philips Corporation.
©
1997 Microchip Technology Inc.
Preliminary
DS21202A-page 1
24C02C
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
V
SS
SDA
SCL
V
CC
A0, A1, A2
WP
PIN FUNCTION TABLE
Function
Ground
Serial Data
Serial Clock
+4.5V to 5.5V Power Supply
Chip Selects
Hardware Write Protect
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins
......................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +4.5V to +5.5V
Commercial (C):
Industrial (I):
Automotive (E):
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
Read
I
CC
Write
I
CCS
Min.
0.7 V
CC
—
0.05 V
CC
—
-10
-10
—
—
—
—
Tamb = 0
°
C to +70
°
C
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to +125
°
C
Max.
—
0.3 V
CC
—
0.40
10
10
10
1
3
50
Units
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
(Note)
I
OL
= 3.0 mA, Vcc = 4.5V
V
IN
= 0.1V to 5.5V, WP = Vss
V
OUT
= 0.1V to 5.5V
V
CC
= 5.0V (Note)
Tamb = 25
°
C, f = 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
V
CC
= 5.5V, SDA = SCL = V
CC
Conditions
All parameters apply across the speci-
fied operating ranges unless otherwise
noted.
Parameter
SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note
: This parameter is periodically sampled and not 100% tested.
DS21202A-page 2
Preliminary
©
1997 Microchip Technology Inc.
24C02C
TABLE 1-3:
AC CHARACTERISTICS
Vcc = 4.5V to 5.5V
Commercial (C):
Industrial (I):
Automotive (E):
Tamb = 0
°
C to +70
°
C
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to +125
°
C
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
All parameters apply across the specified oper-
ating ranges unless otherwise noted.
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Tamb
>
+85
°
C
Min.
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
-40
°
C
≤
Tamb
≤
+85
°
C
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WR
—
—
—
1M
250
50
1.5
—
20 + 0.1 C
B
—
—
1M
250
50
1
—
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
100 pF
(Note 3)
ms Byte or Page mode
cycles 25
°
C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
BUS TIMING DATA
T
F
T
HIGH
T
R
SCL
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
HD
:
STA
T
SP
T
AA
T
BUF
SDA
OUT
©
1997 Microchip Technology Inc.
Preliminary
DS21202A-page 3
24C02C
2.0
2.1
PIN DESCRIPTIONS
SDA Serial Data
3.0
FUNCTIONAL DESCRIPTION
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
The 24C02C supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C02C works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different chip select bit combina-
tions. These inputs must be connected to either V
CC
or
V
SS
.
2.4
WP
This is the hardware write protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.
2.5
Noise Protection
The 24C02C employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
DS21202A-page 4
Preliminary
©
1997 Microchip Technology Inc.
24C02C
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
4.1
Bus not Busy (A)
4.5
Acknowledge
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C02C does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).
FIGURE 4-1:
SCL
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
©
1997 Microchip Technology Inc.
Preliminary
DS21202A-page 5
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