24C01SC/02SC
1K/2K 5.0V I
2
C Serial EEPROMs for Smart Cards
FEATURES
• ISO Standard 7816 pad locations
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• Two-wire serial interface bus, I
2
C
™
compatible
• 100 kHz and 400 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• ESD protection > 4 kV
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• Available for extended temperature ranges
- Commercial (C):
0
°
C to +70
°
C
DIE LAYOUT
V
SS
V
CC
SDA
DC
SCL
BLOCK DIAGRAM
HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24C01SC and
24C02SC are 1K-bit and 2K-bit Electrically Erasable
PROMs with bondpad positions optimized for smart
card applications. The devices are organized as a sin-
gle block of 128 x 8-bit or 256 x 8-bit memory with a
two-wire serial interface. The 24C01SC and 24C02SC
also have page-write capability for up to 8 bytes of data.
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA SCL
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
I
2
C is a trademark of Philips Corporation.
©
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21170A-page 1
24C01SC/02SC
1.0
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Name
V
SS
SDA
SCL
V
CC
DC
PAD FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock
+4.5V to 5.5V Power Supply
Don’t connect
Maximum Ratings*
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
ESD protection on all pads
.....................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +4.5V to +5.5V
Parameter
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CC
Read
Min.
.7 V
CC
—
.05 V
CC
—
-10
-10
—
—
—
—
Commercial (C): Tamb =
Max.
—
.3 V
CC
—
.40
10
10
10
3
1
100
Units
—
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
(Note)
I
OL
= 3.0 mA, V
CC
= 4.5V
V
IN
= .1V to 5.5V
V
OUT
= .1V to 5.5V
V
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
V
CC
= 5.5V
Vcc = 5.5V, SCL = 400 KHz
V
CC
= 5.5V, SDA = SCL = V
CC
0˚C to +70˚C
Conditions
SCL and SDA pads:
High level input voltage
Low level input voltage
Hysteresis of Schmidt trigger inputs
Low level output voltage
Input leakage current (SCL)
Output leakage current (SDA)
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note:
I
CCS
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS21170A-page 2
Preliminary
©
1996 Microchip Technology Inc.
24C01SC/02SC
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 2)
Time the bus must be free
before a new transmission can
start
(Note 1), CB
≤
100 pF
(Note 3)
Byte or Page mode
25
°
C, Vcc = 5V, Block Mode
(Note 4)
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
Remarks
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WR
—
20 +0.1
CB
—
—
10
6
250
50
10
—
ns
ns
ms
cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
SDA
IN
T
HD
:
STA
T
SP
T
AA
SDA
OUT
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
©
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 3
24C01SC/02SC
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24C01SC/02SC supports a bi-directional two-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C01SC/02SC works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C01SC/02SC does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
FIGURE 3-1:
(
A
)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(
A
)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21170A-page 4
Preliminary
©
1996 Microchip Technology Inc.
24C01SC/02SC
4.0
4.1
BUS CHARACTERISTICS
Slave Address
5.0
5.1
WRITE OPERATION
Byte Write
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01SC/02SC, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24C01SC/02SC
(Figure 4-1).
The 24C01SC/02SC monitors the bus for its corre-
sponding slave address all the time. It generates an
acknowledge bit if the slave address was true, and it is
not in a programming mode.
Operation
Read
Write
Control
Code
1010
1010
Chip
Select
XXX
XXX
R/W
1
0
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit, which is a logic low, is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24C01SC/02SC. After
receiving another acknowledge signal from the
24C01SC/02SC, the master device will transmit the
data word to be written into the addressed memory
location. The 24C01SC/02SC acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the
24C01SC/02SC will not generate acknowledge signals
(Figure 5-1).
FIGURE 4-1:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
5.2
Page Write
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
X = Don’t care
The write control byte, word address, and the first data
byte are transmitted to the 24C01SC/02SC in the same
way as in a byte write. But instead of generating a stop
condition, the master transmits up to eight data bytes to
the 24C01SC/02SC, which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the three lower
order address pointer bits are internally incremented by
one. The higher order five bits of the word address
remains constant. If the master should transmit more
than eight words prior to generating the stop condition,
the address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 5-2).
FIGURE 5-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
SDA LINE
S
A
C
K
A
C
K
A
C
K
P
BUS ACTIVITY
FIGURE 5-2:
PAGE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATAn + 1
DATAn + 7
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P
BUS ACTIVITY
©
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 5
Embedded System
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