NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Features
•
High Performance:
-7K
3
CL=2
f
CK
t
CK
t
AC
t
AC
Clock Frequency
Clock Cycle
Clock Access Time
1
Clock Access Time
2
133
7.5
—
5.4
-75B,
CL=3
133
7.5
—
5.4
-8B,
CL=2
100
10
—
6
Units
MHz
ns
ns
ns
1. Terminated load. See AC Characteristics on page 37.
2. Unterminated load. See AC Characteristics on page 37.
3. t
RP
= t
RCD
= 2 CKs
•
•
•
•
•
•
•
•
•
•
•
•
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
8192 refresh cycles/64ms
Random Column Address every CK (1-N Rule)
Single 3.3V
±
0.3V Power Supply
LVTTL compatible
Package: 54-pin 400 mil TSOP-Type II
•
•
•
•
•
•
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BA0/BA1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8
Programmable Wrap: Sequential or Interleave
• -7K parts for PC133 2-2-2 operation
-75B parts for PC133 3-3-3 operation
-8B parts for PC100 2-2-2 operation
Description
The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT
are four-bank Synchronous DRAMs organized as 16Mbit x 4
I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 133MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock. The chip is fabricated with NTC’s
advanced 256Mbit single transistor CMOS DRAM process
technology.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Thirteen row addresses (A0-A12) and two
bank select addresses (BA0, BA1) are strobed with RAS.
Eleven column addresses (A0-A9, A11) plus bank select
addresses and A10 are strobed with CAS. Column address
A11 is dropped on the x8 device, and column addresses A11
and A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A12, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 133MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
REV 1.0
May, 2001
1
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Pin Description
CK
CKE (CKE0, CKE1)
CS
RAS
CAS
WE
BA1, BA0
A0 - A12
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
Input/Output Functional Description
Symbol
CK
CKE, CKE0,
CKE1
CS
RAS, CAS, WE
BA1, BA0
Type
Input
Input
Input
Input
Input
Polarity
Positive
Edge
Active High
Active Low
Active Low
—
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11), when sampled at the rising clock edge. Assume the x4 organization.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10
is low, then BA0 and BA1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
A0 - A12
Input
—
DQ0 - DQ15
Input-
Output
—
DQM
LDQM
UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has
a latency of zero and operates as a word mask by allowing input data to be written if it is low but
blocks the write operation if DQM is high.
—
—
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
V
DD
, V
SS
V
DDQ
V
SSQ
Supply
Supply
REV 1.0
May, 2001
3
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Test/Measurement
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