25C080/160
8K/16K 5.0V SPI
™
Bus Serial EEPROM
FEATURES
•
•
•
•
SPI modes 0,0 and 1,1
3 MHz Clock Rate
Single 5V supply
Low Power CMOS Technology
- Max Write Current: 5 mA
- Read Current: 1.0 mA
- Standby Current: 1
µ
A typical
Organization
- 1024 x 8 for 25C080
- 2048 x 8 for 25C160
16 Byte Page
Self-timed ERASE and WRITE Cycles
Sequential Read
Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Latch
- Write Protect Pin
High Reliability
- Endurance: 10M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000 V
8-pin PDIP/SOIC Packages
Temperature ranges supported
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I):
-40
°
C to +85
°
C
- Automotive (E):
-40˚C to +125˚C
PACKAGE TYPES
PDIP
CS
SO
WP
V
SS
1
25C080/160
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
•
•
•
•
•
•
SOIC
CS
SO
WP
V
SS
1
25C080/160
8
7
6
5
V
CC
HOLD
SCK
SI
2
3
4
•
•
•
BLOCK DIAGRAM
Status
Register
HV Generator
DESCRIPTION
The Microchip Technology Inc. 25C080/160 are 8K and
16K bit Serial Electrically Erasable PROMs. The mem-
ory is accessed via a simple Serial Peripheral Interface
(SPI) compatible serial bus. The bus signals required
are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a chip select (CS) input, allowing any number
of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP).
WP
SI
SO
CS
SCK
HOLD
Sense Amp.
R/W Control
Y Decoder
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Dec
Page Latches
Array
Vcc
Vss
SPI is a trademark of Motorola.
©
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21147F-page 1
25C080/160
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
FIGURE 1-1:
AC TEST CIRCUIT
Vcc
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
......-0.6V to V
CC
+1.0V
Storage temperature .............................-65˚C to 150˚C
Ambient temperature under bias...........-65˚C to 125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins...................................... 4kV
*Stresses above those listed under ‘Maximum ratings’ may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at those or any
other conditions above those indicated in the operational list-
ings of this specification is not implied. Exposure to maximum
rating conditions for extended period of time may affect device
reliability
2.25 K
SO
1.8 K
100 pF
1.2
AC Test Conditions
AC Waveform:
V
LO
= 0.2V
V
HI
= Vcc - 0.2V
V
HI
= 4.0V
(Note 1)
(Note 2)
TABLE 1-1:
Name
CS
SO
SI
SCK
WP
V
SS
V
CC
HOLD
PIN FUNCTION TABLE
Function
Chip Select Input
Serial Data Output
Serial Data Input
Serial Clock Input
Write Protect Pin
Ground
Supply Voltage
Hold Input
Timing Measurement Reference Level
Input
Output
Note 1: For V
CC
≤
4.0V
2: For V
CC
> 4.0V
0.5 V
CC
0.5 V
CC
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted.
V
CC
= 4.5V to 5.5V
Commercial (C): Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Automotive (E): Tamb = -40˚C to +125˚C
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Internal Capacitance
(all inputs and outputs)
Operating Current
Symbol
V
IH1
V
IL1
V
OL
V
OH
I
LI
I
LO
C
INT
ICC write
I
CC
READ
Min
2.0
-0.3
—
V
CC
-0.5
-10
-10
—
Max
V
CC
+1
0.8
0.4
—
10
10
7
Units
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
Test Conditions
I
OL
=2.1 mA
I
OH
=-400
µ
A
CS=V
IH
, V
IN
=Vss to V
CC
CS=V
IH
, V
OUT
=Vss to V
CC
Tamb=25˚C, F
CLK
=3.0 MHz,
V
CC
=5.5V (Note)
V
CC
=5.5V
V
CC
=5.5V; 3 MHz
V
CC
=5.5V; 2 MHz
CS=V
CC
=5.5V; Vin=0V or V
CC
—
5
1
—
—
500
ICC
READ
Standby Current
I
CCS
—
5
Note:
This parameter is periodically sampled and not 100% tested.
DS21147F-page 2
Preliminary
©
1996 Microchip Technology Inc.
25C080/160
2.0
PRINCIPLES OF OPERATION
The 25C080/160 is an 1024/2048 byte EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s midrange
PIC16CXX microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly with soft-
ware.
The 25C080/160 contains an 8-bit instruction register.
The part is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation. If the WPEN bit in the status register is set,
the WP pin must be held high to allow writing to the non-
volatile bits in the status register.
Table 2-1 contains a list of the possible instruction bytes
and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other peripheral
devices on the SPI bus, the user can assert the HOLD
input and place the 25C080/160 in ‘HOLD’ mode. After
releasing the HOLD pin, operation will resume from the
point when the HOLD was asserted.
the WREN or WRDI commands regardless of the state
of write protection on the status register. This bit is read
only.
The
Block Protection (BP0 and BP1)
bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
The
Write Protect Enable (WPEN)
bit is a non-volatile
bit that is available as an enable bit for the WP pin. The
Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the program-
mable hardware write protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write protected, only writes
to non-volatile bits in the status register are disabled.
See Table 2-2 for matrix of functionality on the WPEN
bit and Figure 2-1 for a flowchart of Table 2-2. See
Figure 3-5 for RDSR timing sequence.
TABLE 2-1:
INSTRUCTION SET
2.1
Write Enable (WREN) and Write
Disable (WRDI)
The 25C080/160 contains a write enable latch. This
latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. The following is
a list of conditions under which the write enable latch
will be reset:
•
•
•
•
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
Instruction Instruction
Description
Name
Format
WREN
0000 0110 Set the write enable latch
(enable write operations)
WRDI
0000 0100 Reset the write enable
latch (disable write opera-
tions)
RDSR
0000 0101 Read status register
WRSR
0000 0001 Write status register (write
protect enable and block
write protection bits)
READ
0000 0011 Read data from memory
array beginning at
selected address
WRITE
0000 0010 Write data to memory
array beginning at
selected address
2.2
Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7
WPEN
6 5 4
X X X
3
BP1
2
BP0
1
WEL
0
WIP
The
Write-In-Process (WIP)
bit indicates whether the
25C080/160 is busy with a write operation. When set to
a ‘1’ a write is in progress, when set to a ‘0’ no write is
in progress. This bit is read only.
The
Write Enable Latch (WEL)
bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via
©
1996 Microchip Technology Inc.
Preliminary
DS21147F-page 5
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