24C65
64K 5.0V I
2
C
™
Smart Serial
™
EEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150
µ
A at 5.5V
- Standby current 1
µ
A typical
• Industry standard two-wire bus protocol, I
2
C
™
compatible
• 8 byte page, or byte modes available
• 2 ms typical write cycle time, byte or page
• 64-byte input cache for fast write loads
• Up to eight devices may be connected to the
same bus for up to 512K bits total memory
• Including 400 KHz compatibility
• Programmable block security options
• Programmable endurance options
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 E/W cycles guaranteed for High
Endurance Block
- 100,000 E/W cycles guaranteed for a Stan-
dard Endurance Block
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I)
-40
°
C to +85
°
C
- Automotive (E):
-40
°
C to +125
°
C
PACKAGE TYPES
PDIP
A0
A1
A2
V
SS
1
2
3
4
24C65
8
7
6
5
V
CC
NC
SCL
SDA
SOIC
A0
A1
A2
V
SS
1
2
3
4
24C65
8
7
6
9
V
CC
NC
SCL
SDA
BLOCK DIAGRAM
A0..A2
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM ARRAY
Page Latches
Cache
DESCRIPTION
The Microchip Technology Inc. 24C65 is a “smart” 8K x
8 Serial Electrically Erasable PROM (EEPROM). This
device has been developed for advanced, low power
applications such as personal communications, and
provides the systems designer with flexibility through
the use of many new user-programmable features. The
24C65 offers a relocatable 4K bit block of
ultra-high-endurance memory for data that changes
frequently. The remainder of the array, or 60K bits, is
rated at 1,000,000 ERASE/WRITE (E/W) cycles guar-
anteed. The 24C65 features an input cache for fast
write loads with a capacity of eight pages, or 64 bytes.
This device also features programmable security
I/O
SCL
YDEC
SDA
Vcc
Vss
Sense AMP
R/W Control
options for E/W protection of critical data and/or code of
up to fifteen 4K blocks. Functional address lines allow
the connection of up to eight 24C65's on the same bus
for up to 512K bits contiguous EEPROM memory.
Advanced CMOS technology makes this device ideal
for low-power nonvolatile code and data applications.
The 24C65 is available in the standard 8-pin plastic DIP
and 8-pin surface mount SOIC package.
I
2
C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
©
1996 Microchip Technology Inc.
DS21058G-page 1
This document was created with FrameMaker 4 0 4
24C65
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0..A2
V
SS
SDA
SCL
V
CC
NC
PIN FUNCTION TABLE
Function
User Configurable Chip Selects
Ground
Serial Address/Data I/O
Serial Clock
+4.5V to 5.5V Power Supply
No Internal Connection
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins
..................................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +4.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚ to +85˚C
Automotive (E): Tamb = -40
°
C to +125
°
C
Parameter
Symbol
Min
.7 V
CC
—
.05 V
CC
—
-10
-10
—
—
—
—
Max
—
.3 Vcc
—
.40
10
10
10
3
150
5
Units
V
V
V
V
µ
A
µ
A
pF
mA
µ
A
µ
A
Conditions
A0, A1, A2, SCL and SDA pins:
V
IH
High level input voltage
Low level input voltage
V
IL
Hysteresis of Schmitt Trigger inputs
V
HYS
Low level output voltage
V
OL
Input leakage current
I
LI
Output leakage current
I
LO
Pin capacitance
C
IN
, C
OUT
(all inputs/outputs)
Operating current
I
CC
Write
I
CC
Read
Standby current
I
CCS
Note 1:
Note 1
I
OL
= 3.0 mA
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kH
Z
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V, SCL = SDA =V
CC
Note 1
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS21058G-page 2
©
1996 Microchip Technology Inc.
24C65
TABLE 1-3:
AC CHARACTERISTICS
STD. MODE
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Symbol
Min
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Max
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FAST MODE
Units
Remarks
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Output fall time from V
IH
min to
V
IL
max
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
T
OF
T
SP
T
WR
—
—
—
250
50
5
20 + 0.1
C
B
—
—
250
50
5
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
100 pF
(Note 3)
ms/page (Note 4)
Endurance
High Endurance Block
Rest of Array
10M
1M
—
—
10M
1M
—
—
cycles
25
°
C, Vcc = 5.0V, Block
Mode (Note 5)
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates on a specific
application, please consult the Total Endurance Mode which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
SP
T
AA
SDA
OUT
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
©
1996 Microchip Technology Inc.
DS21058G-page 3
24C65
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24C65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C65 works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C65 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C65) must leave the data line HIGH to
enable the master to generate the STOP condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21058G-page 4
©
1996 Microchip Technology Inc.
24C65
3.6
Device Addressing
4.0
4.1
WRITE OPERATION
Byte Write
A control byte is the first byte received following the start
condition from the master device. The control byte con-
sists of a four bit control code, for the 24C65 this is set
as 1010 binary for read and write operations. The next
three bits of the control byte are the device select bits
(A2, A1, A0). They are used by the master device to
select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a one
a read operation is selected, when set to a zero a write
operation is selected. The next two bytes received define
the address of the first data byte (Figure 4-1). Because
only A12..A0 are used, the upper three address bits
must be zeros. The most significant bit of the most signif-
icant byte is transferred first. Following the start condi-
tion, the 24C65 monitors the SDA bus checking the
device type identifier being transmitted. Upon receiving a
1010 code and appropriate device select bits, the slave
device (24C65) outputs an acknowledge signal on the
SDA line. Depending upon the state of the R/W bit, the
24C65 will select a read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Device Select
Device Address
Device Address
R/W
1
0
Following the start condition from the master, the control
code (four bits), the device select (three bits), and the
R/W bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed slave
receiver (24C65) that a byte with a word address will fol-
low after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the high-order byte of the word address
and will be written into the address pointer of the 24C65.
The next byte is the least significant address byte. After
receiving another acknowledge signal from the 24C65
the master device will transmit the data word to be writ-
ten into the addressed memory location. The 24C65
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24C65 will not generate acknowledge
signals (Figure 4-1).
4.2
Page Write
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
The write control byte, word address and the first data
byte are transmitted to the 24C65 in the same way as in
a byte write. But instead of generating a stop condition
the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24C65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the receipt
of each word, the six lower order address pointer bits are
internally incremented by one. The higher order seven
bits of the word address remain constant. If the master
should transmit more than eight bytes prior to generating
the stop condition (writing across a page boundary), the
address counter (lower three bits) will roll over and the
pointer will be incremented to point to the next line in the
cache. This can continue to occur up to eight times or
until the cache is full, at which time a stop condition
should be generated by the master. If a stop condition is
not received, the cache pointer will roll over to the first
line (byte 0) of the cache, and any further data received
will overwrite previously captured data. The stop condi-
tion can be sent at any time during the transfer. As with
the byte write operation, once the stop condition is
received an internal write cycle will begin. The 64 byte
cache will continue to capture data until a stop condition
occurs or the operation is aborted (Figure 4-2).
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS
S
T
O
P
DATA
SDA LINE
S
A
C
K
0 0
0
A
C
K
A
C
K
P
BUS ACTIVITY
©
1996 Microchip Technology Inc.
DS21058G-page 5
This document was created with FrameMaker 4 0 4
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