24LC04B/08B
4K/8K 2.5V I
2
C
™
Serial EEPROMs
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as two or four blocks of 256 bytes
(2 x 256 x 8) and (4 x 256 x 8)
• 2-wire serial interface bus, I
2
C
™
compatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature ranges
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I):
-40
°
C to +85
°
C
PACKAGE TYPES
PDIP
A0
A1
A2
V
SS
1
24LC04B/08B
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
8-lead
SOIC
A0
A1
A2
V
SS
1
24LC04B/08B
8
7
6
5
V
CC
WP
SCL
SDA
2
3
4
14-lead
SOIC
NC
A0
A1
NC
A2
V
SS
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
V
CC
WP
NC
SCL
SDA
NC
24LC04B/08B
DESCRIPTION
The Microchip Technology Inc. 24LC04B/08B is a 4K or
8K bit Electrically Erasable PROM. The device is orga-
nized as two or four blocks of 256 x 8-bit memory with
a 2-wire serial interface. Low voltage design permits
operation down to 2.5 volts with typical standby and
active currents of only 5
µ
A and 1 mA respectively. The
24LC04B/08B also has a page-write capability for up to
16 bytes of data. The 24LC04B/08B is available in the
standard 8-pin DIP and both 8-lead and 14-lead surface
mount SOIC packages.
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM ARRAY
(2 x 256 x 8) or
(4 X 256 X 8)
PAGE LATCHES
SDA
SCL
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
I
2
C
is a trademark of Philips Corporation.
©
1996 Microchip Technology Inc.
DS21051E-page 1
This document was created with FrameMaker 4 0 4
24LC04B/08B
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
V
SS
SDA
SCL
WP
V
CC
A0, A1, A2
PIN FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
.............. -0.3V to V
CC
+ 1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins
..................................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +2.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial
(I): Tamb = -40˚C to +85˚C
Parameter
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger
Inputs
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
W
RITE
I
CC
R
EAD
I
CCS
Min
.7 V
CC
—
.05 V
CC
—
-10
-10
—
Max
—
.3 V
CC
—
.40
10
10
10
Units
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
(Note)
I
OL
= 3.0mA, V
CC
= 2.5V
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V (Note)
Tamb = 25˚C, Fclk = 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
—
3
—
1
—
30
Standby current
—
100
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS21051E-page 2
©
1996 Microchip Technology Inc.
24LC04B/08B
TABLE 1-3:
AC CHARACTERISTICS
STANDARD
MODE
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Parameter
Symbol
V
CC
= 4.5 - 5.5V
FAST MODE
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
Max
400
—
—
300
300
—
—
—
—
—
900
—
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
Time the bus must be free
before a new transmission can
start
Output fall time from V
IH
min
to V
IL
max
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
24LC04B
24LC08B
T
OF
T
SP
T
WR
—
—
—
250
50
10
20 +0.1
C
B
—
—
250
50
10
ns
ns
ms
(Note 1), C
B
≤
100 pF
(Note 3)
Note 1:
2:
3:
4:
—
10M
—
10M
—
—
1M
—
1M
—
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model whcih can be obtained on our BBS or website.
Byte or Page mode
cycles
25
°
C, Vcc = 5.0V, Block Mode
(Note 4)
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
HD
:
DAT
T
SP
T
AA
T
SU
:
DAT
T
SU
:
STO
T
AA
SDA
OUT
T
HD
:
STA
T
BUF
©
1996 Microchip Technology Inc.
DS21051E-page 3
24LC04B/08B
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24LC04B/08B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC04B/08B
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LC04B/08B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21051E-page 4
©
1996 Microchip Technology Inc.
24LC04B/08B
3.6
Device Addressing
4.0
4.1
WRITE OPERATION
Byte Write
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC04B/08B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). B2 is a don't care for both the
24LC04B and 24LC08B; B1 is a don't care for the
24LC04B. They are used by the master device to select
which of the two or four 256 word blocks of memory are
to be accessed. These bits are in effect the most sig-
nificant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC04B/08B moni-
tors the SDA bus checking the device type identifier
being transmitted, upon a 1010 code the slave device
outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24LC04B/
08B will select a read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC04B/08B. After
receiving another acknowledge signal from the
24LC04B/08B the master device will transmit the data
word to be written into the addressed memory location.
The 24LC04B/08B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LC04B/08B will
not generate acknowledge signals (Figure 4-1).
4.2
Page Write
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1
0
1
0
X
B1
B0
The write control byte, word address and the first data
byte are transmitted to the 24LC04B/08B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24LC04B/08B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
X = Don’t care. B1 is don’t care for 24LC04B.
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
SDA LINE
S
A
C
K
A
C
K
A
C
K
P
BUS ACTIVITY
FIGURE 4-2:
BUS ACTIVITY
MASTER
PAGE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
S
T
O
P
SDA LINE
BUS ACTIVITY
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P
©
1996 Microchip Technology Inc.
DS21051E-page 5
This document was created with FrameMaker 4 0 4
Motor Drive Control（Motor Control）
京公网安备 11010802033920号
EEWORLD
