IDT70V3589S133BC datasheet, PDF

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IDT70V3589S133BC: Description64K X 36 DUAL-PORT SRAM, 15 ns, PBGA256; Categorystorage; File Size356KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V3589S133BC Overview

64K X 36 DUAL-PORT SRAM, 15 ns, PBGA256

IDT70V3589S133BC Parametric

Parameter Name	Attribute value
maximum clock frequency	133 MHz
Number of functions	1
Number of terminals	256
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
Rated supply voltage	3.3 V
Minimum supply/operating voltage	3.15 V
Maximum supply/operating voltage	3.45 V
Processing package description	17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
each_compli	Yes
state	Active
sub_category	SRAMs
ccess_time_max	15 ns
i_o_type	COMMON
jesd_30_code	S-PBGA-B256
jesd_609_code	e0
storage density	2.36E6 bi
Memory IC type	DUAL-PORT SRAM
memory width	36
moisture_sensitivity_level	3
Number of ports	2
Number of digits	65536 words
Number of digits	64K
operating mode	SYNCHRONOUS
organize	64KX36
Output characteristics	3-STATE
Packaging Materials	PLASTIC/EPOXY
ckage_code	LBGA
ckage_equivalence_code	BGA256,16X16,40
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE
serial parallel	PARALLEL
eak_reflow_temperature__cel_	225
wer_supplies__v_	2.5/3.3,3.3
qualification_status	COMMERCIAL
seated_height_max	1.7 mm
standby_current_max	0.0300 Am
standby_voltage_mi	3.15 V
Maximum supply voltage	0.4000 Am
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
terminal coating	TIN LEAD
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
ime_peak_reflow_temperature_max__s_	20
length	17 mm
width	17 mm
dditional_feature	FLOW-THROUGH OR PIPELINED ARCHITECTURE

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HIGH-SPEED 3.3V

128/64K x 36

SYNCHRONOUS

IDT70V3599/89S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B B

WWW

2 3 3

L L R

B B

1 0

R R

1 /0

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d

1c 0c 1b 0b 1a 0a

a b cd

0a 1a 0b 1b

0c 1c 0d 1d

0/1

FT/PIPE

0/1

FT/PIPE

d cba

128K x 36

MEMORY

ARRAY

I/O

- I/O

35 L

Din_L

Din_R

I/O

- I/O

35R

CLK

16L (1)

REPEAT

ADS

CNTEN

CLK

16R

(1)

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

5617 tbl 01

TDI

NOTE:

1. A

is a NC for IDT70V3589.

JTAG

TDO

TCK

TMS

TRST

MAY 2003

DSC 5617/6

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