100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
January 2003
Revised January 2003
100LVELT22
3.3V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
General Description
The 100LVELT22 is a LVTTL/LVCMOS to differential
LVPECL translator operating from a single
+
3.3V supply.
Both outputs of a differential pair should be terminated in
50
Ω
to V
CC
- 2.0V even if only one output is being used. If
an output pair is unused both outputs can be left open
(un-terminated).
The 100 series is temperature compensated.
Features
s
Typical propagation delay of 350 ps
s
<
100 ps skew between outputs
s
Max I
CC
of 28 mA at 25
°
C
s
When TTL input is left Open Q output defaults HIGH
s
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
s
Flow through pinout
s
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
s
Moisture Sensitivity Level 1
s
ESD Performance:
Human Body Model
>
2000V
Machine Model
>
200V
Ordering Code:
Product
Order Number
100LVELT22M
100LVELT22M8
(Preliminary)
Package
M08A
MA08D
Code
KVT22
KR22
Package Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Number Top Mark
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Top View
Pin Descriptions
Pin Name
Q
n
, Q
n
D
0
, D
1
V
CC
GND
Description
LVPECL Differential Outputs
LVTTL/LVCMOS Inputs
Positive Supply
Ground
© 2003 Fairchild Semiconductor Corporation
DS500777
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100LVELT22
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
Input Voltage (V
I
) V
I
≤
V
CC
DC Output Current (I
OUT
)
Continuous
Surge
Storage Temperature (T
STG
)
50 mA
100 mA
0.0V to
+
7.0V
0.0V to
+
7.0V
Recommended Operating
Conditions
Power Supply Operating
LVTTL/LVCMOS Input Voltage
Free Air Operating Temperature (T
A
)
V
CC
=
3.0V to 3.8V
0.0V to V
CC
−
40
°
C to
+
85
°
C
−
65
°
C to
+
150
°
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
LVPECL DC Electrical Characteristics
V
CC
=
3.3V; GND
=
0.0V (Note 2)
Symbol
I
CC
V
OH
V
OL
Parameter
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
2215
1470
−40°C
Min
Typ
Max
28
2420
1745
2275
1490
Min
25°C
Typ
Max
28
2420
1680
2275
1490
Min
85°C
Typ
Max
29
2420
1680
Units
mA
mV
mV
Note 2:
Output parameters vary 1 to 1 with V
CC
. V
CC
can vary
±0.15V.
Note 3:
Outputs are terminated through a 50Ω resistor to V
CC
−
2.0V.
Note:
Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
LVTTL/LVCMOS DC Electrical Characteristics
V
CC
=
3.3V; GND
=
0.0V (Note 4)
Symbol
I
IH
I
IL
V
IK
V
IH
V
IL
Parameter
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
2.0
0.8
T
A
= −40°C
to 85°C
Min
Typ
Max
20
100
−200
−1.2
Units
µA
µA
V
V
V
V
IN
=
2.7V
V
IN
=
V
CC
V
IN
=
0.5V
I
IN
= −18
mA
Condition
Note 4:
V
CC
can vary
±0.15V.
Note:
Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
AC Electrical Characteristics
V
CC
=
3.3V; GND
=
0.0V (Note 5)
Symbol
f
MAX
t
JITTER
t
PLH
/ t
PHL
t
SKEW
t
r
, t
f
Parameter
Maximum Toggle Frequency
Cycle-to-Cycle Jitter
Propagation Delay (Note 6)
Skew
Output-to-Output
Part-to-Part
Output Rise Time Q (20% to 80%)
200
Note 5:
V
CC
can vary
±0.15V.
Note 6:
Specifications for standard LVTTL input signal (see Figure 1).
−40°C
Min
Typ
TBD
TBD
200
350
30
600
100
400
550
200
200
Max
Min
25°C
Typ
TBD
TBD
350
30
600
100
400
500
200
200
Max
Min
85°C
Typ
TBD
TBD
350
30
600
100
400
500
Max
Units
MHz
ps
ps
ps
ns
Figure
Number
Figure 1
Figure 2
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2
100LVELT22
Switching Waveforms
FIGURE 1. LVTTL to Differential LVPECL Propagation Delay
FIGURE 2. Differential Output Edge Rates
3
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100LVELT22
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
www.fairchildsemi.com
4
100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package Number MA08D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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