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SIT1552AI-JE-D17-32.768

Description
Clock Generator
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size737KB,12 Pages
ManufacturerSiTime
Environmental Compliance
Download Datasheet Parametric View All

SIT1552AI-JE-D17-32.768 Overview

Clock Generator

SIT1552AI-JE-D17-32.768 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instruction, BGA4,2X2,40/16
Reach Compliance Codeunknown
Is SamacsysN
JESD-609 codee1
Humidity sensitivity level1
Number of terminals4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
Encapsulate equivalent codeBGA4,2X2,40/16
power supply1.8/3.3 V
Certification statusNot Qualified
Maximum slew rate0.00152 mA
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Base Number Matches1
SiT1552
Features
Smallest (1.2mm
2
), Ultra-Low Power, 32.768 kHz MEMS TCXO
The Smart Timing Choice
The Smart Timing Choice
Applications
32.768 kHz ±5, ±10, ±20 ppm frequency stability options over temp
World’s smallest TCXO in a 1.5 x 0.8 mm CSP
Operating temperature ranges:
• 0°C to +70°C
• -40°C to +85°C
Smart Meters (AMR)
Health and Wellness Monitors
Pulse-per-Second (pps) Timekeeping
RTC Reference Clock
Ultra-low power: <1 µA
Vdd supply range: 1.5V to 3.63V
Improved stability reduces system power with fewer network
timekeeping updates
NanoDrive™ programmable output swing for lowest power and direct
XTAL SoC input interface
Internal filtering eliminates external Vdd bypass cap and saves space
Pb-free, RoHS and REACH compliant
Electrical Characteristics
Parameter
Output Frequency
Frequency Stability Over
Temperature
[1]
(without Initial Offset
[2]
)
Frequency Stability Over
Temperature
(with Initial Offset
[2]
)
Frequency Stability vs Voltage
First Year Frequency Aging
Symbol
Fout
-5.0
F_stab
-10
-20
-10
F_stab
-13
-22
F_vdd
F_aging
-0.75
-1.5
-1.0
Min.
Typ.
32.768
5.0
10
20
10
13
22
0.75
1.5
1.0
ppm
ppm
ppm
µs
pp
ns
RMS
3.63
0.99
1.52
100
180
Start-up Time at Power-up
t_start
300
350
380
ms
V
μA
ms
ppm
ppm
Max.
Unit
kHz
Stability part number code = E
Stability part number code = F
Stability part number code = 1
Stability part number code = E
Stability part number code = F
Stability part number code = 1
1.8V ±10%
1.5V – 3.63V
T
A
= 25°C, Vdd = 3.3V
81920 cycles (2.5 sec), 100 samples
Cycles = 10,000, T
A
= 25°C, Vdd = 1.5V – 3.63V
T
A
= -40°C to +85°C
T
A
= 25°C, Vdd = 1.8V, LVCMOS Output configuration, No Load
T
A
= -40°C to +85°C, Vdd = 1.5V – 3.63V, No Load
Vdd Ramp-Up 0 to 90% Vdd, T
A
= -40°C to +85°C
T
A
= -40°C +60°C, valid output
T
A
= +60°C to +70°C, valid output
T
A
= +70°C to +85°C, valid output
Condition
Frequency and Stability
Jitter Performance (T
A
= over temp)
Long Term Jitter
Period Jitter
35
2.5
Supply Voltage and Current Consumption
Operating Supply Voltage
Core Supply Current
[3]
Power-Supply Ramp
Vdd
Idd
t_Vdd_
Ramp
1.5
Notes:
1. No board level underfill. Measured as peak-to-peak/2. Inclusive of 3x-reflow and ±20% load variation. Tested with Agilent 53132A frequency counter. Due to the
low operating frequency, the gate time must be ≥100 ms to ensure an accurate frequency measurement.
2. Initial offset is defined as the frequency deviation from the ideal 32.768 kHz at room temperature, post reflow.
3. Core operating current does not include output driver operating current or load current. To derive total operating current (no load), add core operating current +
output driver operating current, which is a function of the output voltage swing. See the description titled,
Calculating Load Current.
SiTime Corporation
Rev 1.2
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised November 10, 2014
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