Features
•
Medium-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
100 kHz (2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes are Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
8-lead PDIP and 8-lead JEDEC SOIC Packages
Two-wire
Automotive
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-
trically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead
JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition,
the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.
8K (1024 x 8)
16K (2048 x 8)
Table 1.
Pin Configuration
Pin Name
A0 - A2
SDA
SCL
WP
NC
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
AT24C01A
AT24C02
AT24C04
AT24C08
(1)
AT24C16
(2)
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT24C08A.
2. This device is not recom-
mended for new designs.
Please refer to AT24C16A.
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
3256F–SEEPR–10/04
1
Absolute Maximum Ratings
Operating Temperature......................................−55°C to +125°C
Storage Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Figure 1.
Block Diagram
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.
2
AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no
connects.
The AT24C16 does not use the device address pins, which limits the number of devices
on a single bus to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP):
The AT24C01A/02/04/16 has a Write Protect pin that provides
hardware data protection. The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect pin is connected to V
CC
, the
write protection feature is enabled and operates as shown see Table 2.
Table 2. Write Protect
WP Pin
Status
Part of the Array Protected
24C01A
Full (1K)
Array
24C02
Full (2K)
Array
24C04
Full (4K)
Array
24C08
(1)
Normal
Read/
Write
Operation
24C16
(2)
Upper
Half
(8K)
Array
At V
CC
At GND
Normal Read/Write Operations
Notes:
1. This device is not recommended for new designs. Please refer to AT24C08A.
2. This device is not recommended for new designs. Please refer to AT24C16A.
Memory Organization
AT24C01A, 1K SERIAL EEPROM:
Internally organized with 16 pages of 8 bytes each,
the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM:
Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM:
Internally organized with 32 pages of 16 bytes each,
the 4K requires a 9-bit data word address for random word addressing.
AT24C08, 8K SERIAL EEPROM:
Internally organized with 64 pages of 16 bytes each,
the 8K requires a 10-bit data word address for random word addressing.
AT24C16, 16K SERIAL EEPROM:
Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.
3
3256F–SEEPR–10/04
Table 3.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +2.7V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 4.
DC Characteristics
Applicable over recommended operating range from: T
A
=
−
40°C to +125°C, V
CC
= +2.7V to +5.5V (unless otherwise
noted).
Symbol
V
CC1
V
CC2
I
CC
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Notes:
Parameter
Supply Voltage
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current V
CC
= 2.7V
Standby Current V
CC
= 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
Output Low Level V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
READ at 100 kHz
WRITE at 100 kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
−0.6
V
CC
x 0.7
Test Condition
Min
2.7
4.5
0.4
2.0
1.6
8.0
0.10
0.05
Typ
Max
5.5
5.5
1.0
3.0
4.0
18.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
V
V
mA
mA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
4
AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
Table 5.
AC Characteristics
Applicable over recommended operating range from T
A
=
−
40°C to +125°C, V
CC
= +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C01A/02/04/08,
2.7V
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
AT24C16, 2.7V
Min
Max
400
1.2
0.6
AT24C01A/02/04/08/16,
5.0V
Min
Max
400
1.2
0.6
Units
kHz
µs
µs
50
0.1
1.2
0.6
0.6
0
100
0.9
ns
µs
µs
µs
µs
µs
ns
300
300
0.6
50
ns
ns
µs
ns
5
1M
ms
Write
Cycles
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(2)
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
(3)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(3)
Inputs Fall Time
(3)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C
Min
Max
400
(1)
1.2
0.6
50
0.1
1.2
0.6
0.6
0
100
300
300
0.6
50
5
1M
0.9
50
0.1
1.2
0.6
0.6
0
100
300
300
0.6
50
5
1M
0.9
Notes:
1. The AT24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on the
topside of the package), guarantees 400 kHz (2.5V, 2.7V).
2. This parameter is characterized and is not 100% tested (T
A
= 25°C).
3. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
5
3256F–SEEPR–10/04
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