IDT74LVC162245A datasheet, PDF

IDT74LVC162245A

3.3V CMOS 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

3.3V CMOS 16-BIT

BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

AND 5 VOLT TOLERANT I/O

• Typical t

SK(o)

(Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• V

CC

= 3.3V ± 0.3V, Normal Range

• V

CC

= 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

µ

• All inputs, outputs, and I/O are 5V tolerant

• Available in SSOP, TSSOP, and TVSOP packages

IDT74LVC162245A

FEATURES:

DESCRIPTION:

DRIVE FEATURES:

APPLICATIONS:

• Balanced Output Drivers: ±12mA (A port)

• High Output Drivers: ±24mA (B port)

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

This 16-bit transceiver is built using advanced dual metal CMOS

technology. The LVC162245A is designed for asynchronous communica-

tion between data buses. The control-function implementation minimizes

external timing requirements. This device can be used as two 8-bit

transceivers or one 16-bit transceiver. It allows data transmission from the

A bus to the B bus or from the B bus to the A bus, depending on the logic

level at the direction-control (DIR) input. The output-enable (OE) input can

be used to disable the device so that the buses are effectively isolated. To

ensure the high-impedance state during power up or power down,

OE

should be tied to V

CC

through a pullup resistor; the minimum value of the

resistor is determined by the current-sinking capability of the driver.

All pins can be driven from either 3.3V or 5V devices. This feature allows

the use of this device as a translator in a mixed 3.3V/5V supply system.

The LVC162245A has series resistors in the device output structure of

the “A” port which will significantly reduce line noise when used with light

loads. The driver has been designed to drive ±12mA at the designated

threshold levels. The “B” port has a ±24mA driver.

FUNCTIONAL BLOCK DIAGRAM

1

DIR

1

48

24

2

DIR

25

1

OE

1

A

1

47

2

46

2

OE

2

A

1

36

13

35

1

B

1

2

A

2

B

1

A

2

3

1

B

2

1

A

3

44

5

43

6

33

14

2

B

2

A

3

16

1

B

3

32

2

B

3

2

A

4

17

1

A

4

1

B

4

1

A

5

41

8

2

B

4

2

A

5

30

19

1

B

5

1

A

6

40

9

38

11

2

B

5

2

A

6

1

B

6

2

A

7

1

B

7

29

20

27

22

2

B

6

1

A

7

2

B

7

2

A

8

26

23

1

A

8

37

12

1

B

8

2

B

8

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

1

AUGUST 1999

DSC-4483/1

IDT74LVC162245A

3.3V CMOS 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Description

Max

V

TERM

(2)

Terminal Voltage with Respect to GND

–0.5 to +6.5

–65 to +150

–50 to +50

–50

±100

V

TERM

(3)

Terminal Voltage with Respect to GND

T

STG

I

OUT

I

IK

I

OK

I

CC

I

SS

Storage Temperature

DC Output Current

Continuous Clamp Current,

V

I

< 0 or V

O

< 0

Continuous Current through each

V

CC

or GND

Unit

V

°C

mA

1

DIR

1

B

1

B

2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

OE

1

A

1

A

2

GND

1

B

3

1

B

4

GND

1

A

3

1

A

4

V

CC

1

B

5

1

B

6

V

CC

1

A

5

1

A

6

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. V

CC

terminals.

3. All terminals except V

CC

.

GND

1

B

7

1

B

8

2

B

1

2

B

2

GND

1

A

7

1

A

8

2

A

1

2

A

2

CAPACITANCE

(T

A

= +25°C, F = 1.0MHz)

Symbol

C

IN

C

OUT

C

I/O

Parameter

(1)

Input Capacitance

Output Capacitance

I/O Port Capacitance

Conditions

V

IN

= 0V

V

OUT

= 0V

V

IN

= 0V

Typ.

4.5

6.5

Max.

6

8

Unit

pF

GND

2

B

3

2

B

4

GND

2

A

3

2

A

4

NOTE:

1. As applicable to the device type.

PIN DESCRIPTION

Pin Names

xOE

xDIR

xAx

xBx

Description

Output Enable Input (Active LOW)

Direction Control Output

Side A Inputs or 3-State Outputs

Side B Inputs or 3-State Outputs

V

CC

2

B

5

2

B

6

V

CC

2

A

5

2

A

6

GND

2

B

7

2

B

8

2

DIR

GND

2

A

7

2

A

8

2

OE

FUNCTION TABLE

(EACH 8-BIT SECTION)

(1)

Inputs

xOE

xDIR

L

H

X

Outputs

B Data to A Bus

A Data to B Bus

Isolation

SSOP/ TSSOP/ TVSOP

TOP VIEW

L

H

NOTE:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

2

IDT74LVC162245A

3.3V CMOS 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: T

A

= –40°C to +85°C

Symbol

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

OFF

V

IK

V

H

I

CCL

I

CCH

I

CCZ

∆I

CC

High Impedance Output Current

(3-State Output pins)

Input/Output Power Off Leakage

Clamp Diode Voltage

Input Hysteresis

Quiescent Power Supply Current

V

CC

= 0V, V

IN

or V

O

≤

5.5V

V

CC

= 2.3V, I

IN

= –18mA

V

CC

= 3.3V

V

CC

= 3.6V

V

IN

= GND or V

CC

—

–0.7

100

—

±50

–1.2

—

10

500

µA

V

mV

µA

V

CC

= 3.6V

V

O

= 0 to 5.5V

—

±10

µA

Parameter

Input HIGH Voltage Level

Input LOW Voltage Level

Input Leakage Current

V

CC

= 2.3V to 2.7V

V

CC

= 2.7V to 3.6V

V

CC

= 2.3V to 2.7V

V

CC

= 2.7V to 3.6V

V

CC

= 3.6V

V

I

= 0 to 5.5V

Test Conditions

Min.

1.7

2

—

Typ.

(1)

—

Max.

—

0.7

0.8

±5

µA

V

Unit

V

Quiescent Power Supply Current

Variation

3.6

≤

V

IN

≤

5.5V

(2)

One input at V

CC

- 0.6V, other inputs at V

CC

or GND

µA

NOTES:

1. Typical values are at V

CC

= 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUT DRIVE CHARACTERISTICS (A PORT)

Symbol

V

OH

Parameter

Output HIGH Voltage

V

CC

= 2.3V

V

CC

= 2.7V

V

CC

= 3V

V

OL

Output LOW Voltage

V

CC

= 2.3V to 3.6V

V

CC

= 2.3V

V

CC

= 2.7V

V

CC

= 3V

Test Conditions

(1)

V

CC

= 2.3V to 3.6V

I

OH

= – 0.1mA

I

OH

= – 4mA

I

OH

= – 6mA

I

OH

= – 4mA

I

OH

= – 8mA

I

OH

= – 6mA

I

OH

= – 12mA

I

OL

= 0.1mA

I

OL

= 4mA

I

OL

= 6mA

I

OL

= 4mA

I

OL

= 8mA

I

OL

= 6mA

I

OL

= 12mA

Min.

V

CC

– 0.2

1.9

1.7

2.2

2

2.4

2

—

Max.

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

V

Unit

V

NOTE:

1. V

IH

and V

IL

must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V

CC

range.

T

A

= – 40°C to + 85°C.

3

IDT74LVC162245A

3.3V CMOS 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

OUTPUT DRIVE CHARACTERISTICS (B PORT)

Symbol

V

OH

Parameter

Output HIGH Voltage

V

CC

= 2.3V

V

CC

= 2.3V

V

CC

= 2.7V

V

CC

= 3V

V

CC

= 3V

V

OL

Output LOW Voltage

V

CC

= 2.3V to 3.6V

V

CC

= 2.3V

V

CC

= 2.7V

V

CC

= 3V

I

OH

= – 24mA

I

OL

= 0.1mA

I

OL

= 6mA

I

OL

= 12mA

I

OL

= 12mA

I

OL

= 24mA

Test Conditions

(1)

V

CC

= 2.3V to 3.6V

I

OH

= – 0.1mA

I

OH

= – 6mA

I

OH

= – 12mA

Min.

V

CC

– 0.2

2

1.7

2.2

2.4

2

—

Max.

—

0.2

0.4

0.7

0.4

0.55

V

Unit

V

NOTE:

1. V

IH

and V

IL

must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V

CC

range.

T

A

= – 40°C to + 85°C.

OPERATING CHARACTERISTICS, V

CC

= 3.3V ± 0.3V, T

A

= 25°C

Symbol

C

PD

C

PD

Parameter

Power Dissipation Capacitance per Transceiver Outputs enabled

Power Dissipation Capacitance per Transceiver Outputs disabled

Test Conditions

C

L

= 0pF, f = 10Mhz

Typical

Unit

pF

SWITCHING CHARACTERISTICS (A PORT)

(1)

Symbol

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

SK

(o)

Parameter

Propagation Delay

xBx to xAx

Output Enable Time

xOE to xAx

Output Disable Time

xOE to xAx

Output Skew

(2)

V

CC

= 2.7V

Min.

Max.

1.5

5.7

1.5

7.9

8.3

V

CC

= 3.3V ± 0.3V

Min.

Max.

1.5

4.8

1.5

2.2

6.3

7.4

500

Unit

ns

ps

—

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. T

A

= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

SWITCHING CHARACTERISTICS (B PORT)

(1)

Symbol

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

SK

(o)

Parameter

Propagation Delay

xAx to xBx

Output Enable Time

xOE to xBx

Output Disable Time

xOE to xBx

Output Skew

(2)

V

CC

= 2.7V

Min.

Max.

1.5

4.7

1.5

6.7

7.1

V

CC

= 3.3V ± 0.3V

Min.

Max.

1

4

1.5

5.5

6.6

500

Unit

ns

ps

—

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. T

A

= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

4

IDT74LVC162245A

3.3V CMOS 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

TEST CONDITIONS

Symbol

V

LOAD

V

IH

V

T

V

LZ

V

HZ

C

L

V

CC(1)

= 3.3V±0.3V

6

2.7

1.5

300

50

V

CC

500Ω

Pulse

(1, 2)

Generator

V

IN

D.U.T.

R

T

500Ω

C

L

LVC Link

V

CC(1)

= 2.7V

6

2.7

1.5

300

50

V

CC(2)

= 2.5V±0.2V

2 x Vcc

Vcc

Vcc / 2

150

30

Unit

V

mV

pF

V

LOAD

Open

GND

SAME PHASE

INPUT TRANSITION

t

PLH

OUTPUT

t

PLH

OPPOSITE PHASE

INPUT TRANSITION

t

PHL

t

PHL

V

IH

V

T

0V

V

OH

V

T

V

OL

V

IH

V

T

0V

LVC Link

Propagation Delay

ENABLE

CONTROL

INPUT

t

PZL

OUTPUT

SWITCH

NORMALLY

CLOSED

LOW

t

PZH

OUTPUT

SWITCH

NORMALLY

OPEN

HIGH

V

LOAD/2

V

T

t

PHZ

V

T

0V

t

PLZ

DISABLE

V

IH

V

T

0V

V

LOAD/2

V

OL+

V

LZ

V

OL

V

OH

V

OH-

V

HZ

0V

LVC Link

V

OUT

Test Circuit for All Outputs

DEFINITIONS:

C

L

= Load capacitance: includes jig and probe capacitance.

R

T

= Termination resistance: should be equal to Z

OUT

of the Pulse Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate

≤

10MHz; t

F

≤

2.5ns; t

R

≤

2.5ns.

2. Pulse Generator for All Pulses: Rate

≤

10MHz; t

F

≤

2ns; t

R

≤

2ns.

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

Enable and Disable Times

SWITCH POSITION

Test

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other Tests

Switch

V

LOAD

GND

Open

V

IH

V

T

0V

V

OH

V

T

V

OL

V

OH

V

T

V

OL

t

PLH2

t

PHL2

LVC Link

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS

CONTROL

SYNCHRONOUS

CONTROL

t

SU

t

H

t

REM

t

SU

t

H

V

IH

V

T

0V

V

IH

V

T

0V

V

IH

V

T

0V

V

IH

V

T

0V

LVC Link

INPUT

Set-up, Hold, and Release Times

LOW-HIGH-LOW

PULSE

t

W

HIGH-LOW-HIGH

PULSE

V

T

LVC Link

t

PLH1

t

PHL1

OUTPUT 1

V

T

t

SK

(x)

t

SK

(x)

OUTPUT 2

t

SK

(x)

= t

PLH2

-

t

PLH1

or

t

PHL2

-

t

PHL1

Pulse Width

Output Skew - t

SK

(

X

)

NOTES:

1. For t

SK

(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t

SK

(b) OUTPUT1 and OUTPUT2 are in the same bank.

5

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