PCI, PCI-to-PCI, I/O-to-I/O transfers, and I/O support of
scatter/gather
– Supports chaining via linked lists of records
– Supports unaligned transfers
– Supports burst transfers
– Programmable burst size
x
PCI Bridge
– 32-bit PCI, up to 33 MHz
– Revision 2.1 compliant
– Target and master
– Host or satellite
– Three slot PCI arbiter, on-chip
– Serial EEPROM support, for loading configuration
registers
x
3.3V core operation
x
3.3V I/O operation with 5V tolerant I/O
x
208 pin PQFP package
Block Diagram
CPU I/F
Timer, UART,
Interrupt Modules
EDO/SDRAM
Control
Memory I/O
Control
Data & Address bus
SDRAM/EDODRAM Control
Memory &
I/O Control
DMA Channels
RC32134
PCI I/F and Bridge
PCI Bus
The IDT logo is a registered trademark. RC64145, RC64474, RC64475, RC32134, RC4600, RC4640, RC4650, RC4700, RC3041, RC3051, RC3052, RC3081, RISController, and RISCore are trademarks of Inte-
grated Device Technology, Inc.
1 of 25
2000 Integrated Device Technology, Inc.
April 9, 2001
DSC 5602
IDT79RC32134
Description
The IDT79RC32134 is a high performance system controller chip
that supports IDT’s RISCore32300 CPU family. The RC32134 offers a
direct connection to IDT’s RC32364 32-bit embedded microprocessor.
The RC32134 provides the system logic for boot memory, main memory,
I/O, and PCI. It also includes on-chip peripherals such as DMA chan-
nels, reset circuitry, interrupts, timers, and UARTs. Together, the
RC32364 CPU and the RC32134 system controller form a complete
CPU subsystem for embedded designs.
Figure 1 illustrates the typical system implementation, based on the
RC32364 CPU and the RC32134 system controller. The RC32134 inter-
faces directly to the RC32364 and provides all of the necessary control
and address signals to drive the external memory and I/O. Note that,
depending on the loading of the CPU data bus, external data buffers
could be used to reduce the loading and isolate different memory
regions. As illustrated in the system block diagram, the memory and I/O
data path is external to the RC32134.
and from the internal peripherals and registers is internal to the
RC32134.
Memory Controller.
The Memory Controller on the RC32134
provides all of the address buses and control signals for interfacing the
RC32364 CPU to standard SRAM, PROM, FLASH, and I/O and
includes the boot PROM interface. The memory controller provides six
individual chip selects and supports 8,16, and 32-bit wide memory and I/
Os. Two chip selects have highly configurable memory address ranges,
allowing selection of various memory types and widths to be supported.
The RC32134 provides controls for optional external data transceivers
for systems that require fast signalling with large loads.
SDRAM Controller.
The SDRAM controller optimization provides
higher throughput while using available DRAM technology. The SDRAM
control register directly manages four banks of 32-bit physical non-inter-
leaved memory. Each bank is 32-bits wide and supports a maximum of
64 MB per bank. Total memory support is 256 MB. The SDRAM
controller has a built in refresh generator.
EDO DRAM Controller.
The RC32134 EDO DRAM Controller
supports up to 4 banks of non-interleaved 32-bit wide EDO DRAMs.
Most of the EDO DRAM pins are shared with the SDRAM controller, and
as such, the two operations can not be simultaneously enabled. Selec-
tion between SDRAM or EDO DRAM is made at boot-time through
system software operations. The EDO supports 256 MB total of EDO
DRAM. The EDO controller has a built in refresh generator.
PCI Interface.
To transfer data between main memory and the PCI
bus, the RC32134 incorporates a PCI interface. At reset time the PCI
interface can be configured as either a host or satellite interface. The
PCI interface supports 32-bit PCI at up to 33MHz and is PCI Specifica-
tion, Revision 2.1 compliant.
Device Overview
The RC32134 interfaces directly to the RC32364’s system bus. The
RC32134 latches the address from the RC32364 internally and decodes
it to detect which memory, I/O, or on-chip peripheral is being accessed,
per the internal address map of the RC32134. The RC32134 generates
all necessary control signals and address buses to the external memory
and I/O. For main memory, I/O, on-chip peripherals, registers, and PCI,
the RC32134 divides the physical address space into 14 different
regions.
The data path for the local memory and peripherals (with the excep-
tion of PCI) is external to the RC32134. The data path from the PCI bus
RC32364
Clock
RC32134
CPU I/F
Serial
PIO
Timers,
UART,
Interrupt Ctl
DMA
Channels
DRAM Ctl
Memory &
I/O Ctl
Address &
Control
Memory
& I/O
SDRAM
32-bit Data
Bus
PCI Bridge with Arbiter
32-bit, 33Mhz PCI Bus
Figure 1 System Block Diagram
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April 9, 2001
IDT79RC32134
As a PCI master, the RC32134 can generate memory, I/O, or config-
uration cycles for direct local-to-PCI bus accesses. The PCI interface
incorporates a 3-slot PCI bus arbiter, which includes fixed and round
robin arbitration modes.
As a PCI target, the RC32134 allows access to its internal registers
and to the RISCore32300 local bus through the PCI I/O read and write,
or Memory read and write commands. The RC32134 PCI interface
supports swapping little endian data to big endian, when the CPU
subsystem is configured as a big endian system. For more information
on the PDCI interface, please refer to the PCI Specification, Revision
2.1.
DMA Controller.
Four general purpose DMA channels move data
between source and destination ports. Source and destination ports can
be system memory, PCI or I/O devices. Any of the four channels can be
used for PCI initiator reads or writes. All four channels support a
descriptor structure, to allow efficient data scatter/gather. The DMA
controller supports swapping of data between big and little endian
memory and I/O subsystems by memory region. It also supports quad-
word burst transfers. All external 16 and 8-bit memory I/Os are treated
as memory-mapped, word-aligned devices.
Expansion Interrupt Controller.
The Expansion Interrupt Controller
provides the interrupt logic for software to analyze the various RC32134
generated system interrupts and adds to the control already provided
through the CP0 registers of the RC32364. Each system interrupt is
registered and the pending status provided through this feature. The
pending status can then be used to automatically generate a hardware
interrupt to the CPU via individual mask bits. The pending interrupt
status can also be optionally set or cleared by a direct software write.
PIO.
Programmable I/O (PIO) pins are provided on the RC32134 so
that any unused peripheral pins can be programmed for use as general
purpose discrete I/O pins. These PIO pins can be software programmed
as bidirectional lines, allowing pin values to be software programmed in
output mode and software readable while in the input mode. The PIO
pins can also be used as a source of interrupts to the CPU. Maximum
Interfacing flexibility is thus provided without requiring extensive modifi-
cations to the board.
UART.
The RC32134 incorporates two 16550 (an enhanced version
of the 16450) compatible UARTs. To relieve the CPU of software over-
head, the 16550 UART can be put into FIFO mode, allowing execution
of either 16450 or 16550 compatible software. Two sets of 16-byte
FIFOs are enabled during the 16550 mode: one set in the receive data
path and one set in the transmit data path. A baud rate generator is
included that divides the system clock by 1 to 64K and provides a 16X
clock for driving the transmitter and receiver logic.
Timers/Counters.
Three on-chip 32-bit general purpose Timers are
provided on the RC32134. Each timer consists of both a count and a
compare register. The count register resets to zero and then counts
upward until it equals the compare register. When the count and
compare registers are equal, the TC_n output is asserted and the count
is then reset to zero.
JTAG.
Board-level manufacturing debugging is facilitated through
implementation of a fully compliant IEEE std. 1149.1 JTAG Boundary
Scan interface.
Thermal Considerations
The RC32134 is guaranteed in a case temperature range of 0°C to
+90°C, for commercial temperature devices; - 40°C to +90°C for indus-
trial temperature devices. The speed (power) of the device and airflow
conditions affect the equivalent ambient temperature conditions that will
meet this specification. The equivalent allowable ambient temperature,
T
A
, can be calculated using the thermal resistance from case to ambient
(∅
CA
) of the given package. The following equation relates ambient and
case temperatures:
T
A
= T
C
- P *
∅
CA
where P is the maximum power consumption at hot temperature,
calculated by using the maximum I
CC
specification for the device.
Typical values for
∅
CA
at various airflows are shown in Table 1
∅
CA
Airflow (ft/min)
208 PQFP
0
18
200
14
400
11
600
9
800
8
1000
7
Table 1 Thermal Resistance (∅CA) at Various Airflows
Revision History:
July 21, 1999:
Changed the following: Thermal Resistance values; Table 2, Pin
Descriptions; Logic diagram - RC32134; Clock parameter temperature
from 85 to 90 degrees; AC timing characteristics - RC32134; DC elec-
trical characteristics; Power consumption - RC32134; Absolute
maximum ratings diagram; Pin-out 208-PQFP table; RC32134 alternate
signal functions.
September 2, 1999:
Corrected package drawing from 144-pin to
208-pin.
November 1, 1999:
Removed Maximum column from Power
Consumption table.
November 9, 1999:
Moved pin 208 (sdram_245_oe_n) from Low
drive to High drive in DC Electrical Characteristics Table.
April 28, 2000:
Added Mode Configuration Interface Reset
Sequence figure on page 14.
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April 9, 2001
IDT79RC32134
January 6, 2000:
– Reordered
Alternate Signals for the PIO Interface in Table 2
and changed pci_eeprom_mdi to pci_eeprom_mdo.
–
Switched alternate pin signals for pci_eeprom_mdo and
pci_eeprom_mdi in PCI Interface section of Table 2.
–
Switched alternate pin signals for uart_rx and uart_tx in UART
Interface section of Table 2.
–
In RC32134 Alternate Signal Functions table, changed pin
designations under Alt #1 column for pins 22 - 29.
–
Changed 64145 references to 32134 in the Note section of the
AC Timing Characteristics table.
–
Updated the User Manual Timing Diagram Reference column
in the AC Timing Characteristics table.
March 20, 2000:
Changed PCI speed to 33 MHz.
June 20, 2000:
Values were revised for three local memory/periph-
eral bus signals in the AC Timing Characteristics table.
July 12, 2000:
Revised Tsu and Thld symbol numbers in UART
section of AC Timing Characteristics table and revised reference to
timing diagram.
April 9, 2001:
In the Local Memory/Peripheral bus section of the AC
Timing Characteristics table, deleted cpu_coldreset_n associated with
Tsu4.
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April 9, 2001
IDT79RC32134
Pin Description Table
The following table lists the pins provided on the RC32134. Note that several pins are multiplexed and have been assigned alternate functions.
These pins are designated and defined accordingly throughout this table. Also note that those pin names followed by _n are active-low signals.
Pin Name
Type Alternate Signal(s)
Description
Local Memory and Peripheral Pins
cpu_ad[31:0]
I/O
Not applicable
CPU Address/Data Bus
This is the RC32134’s primary multiplexed and bidirectional address and data bus. The RC32134
latches this bus internally and uses it to generate the necessary address lines to the external memory
and peripherals. If the transaction is a write, the CPU then drives data on cpu_ad(31:0). During CPU
generated transactions, the CPU drives Address(31:4) into the cpu_ad bus, during its address phase.
During DMA generated transactions (or RC32134 internal register reads), the address phase is
unused and the chip drives data during a write.
CPU LSB Address Bus
During CPU generated transactions, the CPU drives Address(3:2) onto the cpu_addr bus. The
RC32134 does not internally use the cpu_addr bus during the data phase. However, 8- or 16-bit
memory or I/O systems must attach these two pins instead of mem_addr(3:2).
CPU Address Latch Enable
During CPU generated transactions, this signal indicates that the cpu_ad (31:0) is driving a valid
address and can be latched internally by the RC32134.
CPU Cycle In Progress
During CPU generated transactions, this active-low signal indicates that a bus transaction is active.
An external pullup resistor is required.
CPU Write Status
During CPU generated transactions, this active-low signal indicates whether or not a write is occur-
ring. If a write is not occurring, then the implication is that a read is in progress.
CPU Byte Enable Bus
During CPU generated transactions, these active-low signals indicate which byte lanes are in use.
Note:
The table below indicates which cpu_be_n signal corresponds to which byte lane, whether or
not the system is in big or little endian mode
Data Bits
cpu_be_n[0]
cpu_be_n[1]
cpu_be_n[2]
cpu_be_n[3]
cpu_ack_n
O
Not applicable
7:0
15:8
23:16
31:24
cpu_addr[3:2]
I
Not applicable
cpu_ale
I
Not applicable
cpu_cip_n
I
Not applicable
cpu_wr_n
I
Not applicable
cpu_be_n[3:0]
I
Not applicable
CPU Acknowledge
During CPU generated transactions, this active-low signal is generated by the RC32134 to indicate
that the present data have been accepted.
CPU Last Data
During CPU generated transactions, this active-low signal indicates during the data phase that the
present data is the last data.
CPU Bus Error
During both CPU and DMA generated transactions, this active-low signal indicates that a bus error
has occurred. This signal can also be optionally attached to an interrupt line.
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