MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P–channel
and N–channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide–by–N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide–by–N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase–locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14526BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MC14526B
AWLYWW
1
Unit
V
V
mA
mW
°C
°C
°C
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
14526B
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Logic Edge–Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition of Inhibit
•
Asynchronous Preset Enable
•
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
AWLYYWW
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±10
500
– 55 to +125
– 65 to +150
260
ORDERING INFORMATION
Device
MC14526BCP
MC14526BDW
MC14526BDWR2
MC14526BF
Package
PDIP–16
SOIC–16
SOIC–16
SOEIAJ–16
Shipping
2000/Box
47/Rail
1000/Tape & Reel
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
v
v
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14526B/D
MC14526B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
Characteristic
Symbol
V
OL
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
V
IH
5.0
10
15
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
—
5.0
10
15
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
—
—
—
—
—
—
—
—
—
±
0.1
—
5.0
10
20
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
—
—
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
—
—
—
—
—
—
—
±
0.1
7.5
5.0
10
20
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
—
—
—
—
—
—
—
—
—
±
1.0
—
150
300
600
mAdc
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
mAdc
Min
—
—
—
– 55
_
C
25
_
C
125
_
C
Max
Min
—
—
—
Typ
(4.)
0
0
0
Max
Min
—
—
—
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
“0” Level
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
V
IL
—
—
—
—
—
—
2.25
4.50
6.75
—
—
—
V
OH
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Vdc
Sink
I
in
C
in
I
DD
µAdc
pF
µAdc
I
T
I
T
= (1.7
µA/kHz)
f + I
DD
I
T
= (3.4
µA/kHz)
f + I
DD
I
T
= (5.1
µA/kHz)
f + I
DD
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
µA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
http://onsemi.com
3
MC14526B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Symbol
V
DD
5.0
10
15
Min
—
—
—
Typ
(8.)
100
50
40
Max
200
100
80
Unit
ns
t
TLH
,
t
THL
(Figures 4, 5)
Propagation Delay Time (Inhibit Used as Negative
Edge Clock)
Clock or Inhibit to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 465 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 135 ns
Clock or Inhibit to “0”
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 155 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 87 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
Propagation Delay Time
Pn to Q
Propagation Delay Time
Reset to Q
Propagation Delay Time
Preset Enable to “0”
Clock or Inhibit Pulse Width
t
PLH
,
t
PHL
(Figures 4, 7)
t
PHL
(Figure 8)
t
PHL
,
t
PLH
(Figures 4, 9)
t
w
(Figures 5, 6)
Clock Pulse Frequency (with PE = low)
f
max
(Figures 4, 5, 6)
Clock or Inhibit Rise and Fall Time
t
r
,
t
f
(Figures 5, 6)
t
su
(Figure 10)
Hold Time
Preset Enable to Pn
Preset Enable Pulse Width
t
h
(Figure 10)
t
w
(Figure 10)
Reset Pulse Width
t
w
(Figure 8)
Reset Removal Time
t
rem
(Figure 8)
t
PLH
,
t
PHL
(Figures 4, 5, 6)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
250
100
80
—
—
—
—
—
—
90
50
40
30
30
30
250
100
80
350
250
200
10
20
30
550
225
160
240
130
100
260
120
100
250
110
80
220
100
80
125
50
40
2.0
5.0
6.6
—
—
—
40
15
10
– 15
–5
0
125
50
40
175
125
100
– 110
– 30
– 20
1100
450
320
480
260
200
520
240
200
500
220
160
440
200
160
—
—
—
1.5
3.0
4.0
15
5
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
MHz
µs
Setup Time
Pn to Preset Enable
ns
ns
ns
ns
ns
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
http://onsemi.com
4
京公网安备 11010802033920号
EEWORLD
