1516SC400501A datasheet, PDF - EEWORLD Datasheet

1516SC400501A: DescriptionPassive Delay Line, 1-Func, 5-Tap, True Output, Hybrid, SMD-8; Categorylogic logic; File Size53KB，1 Pages; ManufacturerData Delay Devices; Environmental Compliance

Download Datasheet Parametric View All

1516SC400501A Overview

Passive Delay Line, 1-Func, 5-Tap, True Output, Hybrid, SMD-8

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	compliant
Is Samacsys	N
Other features	MAX RISE TIME CAPTURED
JESD-30 code	R-XDSO-G8
Logic integrated circuit type	PASSIVE DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Output impedance nominal value (Z0)	500 Ω
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	7.366 mm
surface mount	YES
technology	HYBRID
Terminal form	GULL WING
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	40 ns
width	6.858 mm
Base Number Matches	1

Everyone loves Yidianli - forward to get gifts!: [b][color=#000000][font=宋体]Everyone loves Easy Power Supply[/font][font=Cambria]——[/font][font=宋体]Repost and get a gift! [/font][/color]Activity theme: Everyone loves Easy Power Supply——Repost and get...; wangshi_8678 Analogue and Mixed Signal

Does anyone have a video tutorial on Xiaomei's FPGA design ideas and verification methods?: Does anyone have a video tutorial on Xiaomei's FPGA design ideas and verification methods? Thank you....; 张正发 FPGA/CPLD

Create a flexible EDGE data receiver(Part 1): Today''s integrated solutions don''t necessarily have to result in a high level of complexity. The introduction of new wireless standards often places tremendous pressure on the underlying technologie...; fly RF/Wirelessly

[Project source code] Altera FPGA enables the on-chip pull-up resistor function of the pin: This article and design code were written by FPGA enthusiast Xiao Meige. Without the author's permission, this article is only allowed to be copied and reproduced on online forums, and the original au...; 小梅哥 FPGA/CPLD

Recommended Espressif ESP32+WT32-SC01: Since its launch, Espressif's ESP32 has revolutionized WIFI and Bluetooth applications. The ESP32R Wi-Fi distance can reach 40 meters and the Bluetooth distance can reach 10 meters (this distance is f...; wireless-tag Domestic Chip Exchange

RISC-V MCU Development (10): File Version Management: Version Control System is an indispensable part of most IDEs. Its main function is to record changes in the content of one or more files, such as file modification and deletion, so that developers can...; Moiiiiilter MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components