IDC Low Inductance Capacitors (RoHS)
0306/0612/0508 IDC (InterDigitated Capacitors)
GENERAL DESCRIPTION
Inter-Digitated Capacitors (IDCs) are used for both semiconductor
package and board level decoupling. The equivalent series
inductance (ESL) of a single capacitor or an array of capacitors in
parallel determines the response time of a Power Delivery Network
(PDN). The lower the ESL of a PDN, the faster the response time.
A designer can use many standard MLCCs in parallel to reduce
ESL or a low ESL Inter-Digitated Capacitor (IDC) device. These IDC
devices are available in versions with a maximum height of 0.95mm
or 0.55mm.
IDCs are typically used on packages of semiconductor products
with power levels of 15 watts or greater. Inter-Digitated Capacitors
are used on CPU, GPU, ASIC, and ASSP devices produced on
0.13μ, 90nm, 65nm, and 45nm processes. IDC devices are used
on both ceramic and organic package substrates. These low ESL
surface mount capacitors can be placed on the bottom side or the
top side of a package substrate. The low profile 0.55mm maximum
height IDCs can easily be used on the bottom side of BGA
packages or on the die side of packages under a heat spreader.
IDCs are used for board level decoupling of systems with speeds of
300MHz or greater. Low ESL IDCs free up valuable board space by
reducing the number of capacitors required versus standard
MLCCs. There are additional benefits to reducing the number of
capacitors beyond saving board space including higher reliability
from a reduction in the number of components and lower
placement costs based on the need for fewer capacitors.
The Inter-Digitated Capacitor (IDC) technology was developed by
AVX. This is the second family of Low Inductance MLCC products
created by AVX. IDCs are a cost effective alternative to AVX’s first
generation low ESL family for high-reliability applications known as
LICA (Low Inductance Chip Array).
AVX IDC products are available with a lead-free finish of plated
Nickel/Tin.
0612
+
–
+
–
0508
0306
TYPICAL IMPEDANCE
10
Impedance (Ohms)
MLCC_1206
1
LICC_0612
0.1
IDC_0612
0.01
0.001
1
10
100
1000
Frequency (MHz)
HOW TO ORDER
W
Style
LEAD-FREE COMPATIBLE
COMPONENT
3
L
1
6
D
225
M
A
T
3
A
Thickness
Max. Thickness
mm (in.)
IDC
Low
Number Voltage
Case
Inductance
of
4 = 4V
Size
Terminals
6 = 6.3V
2 = 0508
1 = 8 Terminals Z = 10V
3 = 0612
Y = 16V
4 = 0306
3 = 25V
Dielectric Capacitance Capacitance Failure Termination Packaging
Tolerance Rate
T = Plated Ni
C = X7R
Code (In pF)
Available
D = X5R 2 Sig. Digits + M = ±20% A = N/A
and Sn
1=7" Reel
Number of
Z = X7S
3=13" Reel
Zeros
A=Standard
S=0.55 (0.022)
NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers.
PERFORMANCE CHARACTERISTICS
Capacitance Tolerance
Operation
Temperature Range
Temperature Coefficient
Voltage Ratings
Dissipation Factor
±20% Preferred
X7R = -55°C to +125°C
X5R = -55°C to +85°C
X7S = -55°C to +125°C
±15% (0VDC), ±22% (X7S)
4, 6.3, 10, 16, 25 VDC
≤ 6.3V = 6.5% max;
10V = 5.0% max;
≥ 16V = 3.5% max
100,000MΩ min, or 1,000MΩ per
μF min.,whichever is less
Dielectric Strength
CTE (ppm/C)
Terminations
Available
No problems observed after 2.5 x RVDC
for 5 seconds at 50mA max current
12.0
Thermal Conductivity
4-5W/M K
Plated Nickel and Solder
Insulation Resistance
(@+25°C, RVDC)
72
+
–
+
–
IDC Low Inductance Capacitors (RoHS)
0306/0612/0508 IDC (InterDigitated Capacitors)
SIZE
Max.
mm
Thickness (in.)
WVDC
Cap
(μF)
0.010
0.022
0.033
0.047
0.068
0.10
0.22
0.33
0.47
0.68
1.0
1.5
2.2
3.3
4
0306
0.55
(0.022)
6.3
4
Thin 0508
0.55.
(0.022)
6.3
10
16
25
4
0508
0.95
(0.037)
6.3
10
16
25
4
Thin 0612
0.55
(0.022)
6.3 10
16
4
0612
0.95
(0.037)
6.3
10
16
25
4
THICK 0612
1.22
(0.048)
6.3
10
16
PHYSICAL DIMENSIONS AND PAD LAYOUT
W
Consult factory for
additional requirements
= X7R
= X5R
= X7S
T
D
E
P
BW
A
B
C
BL
L
PHYSICAL CHIP DIMENSIONS
SIZE
0306
0508
0612
millimeters (inches)
BL
0.20 ± 0.10
(0.008± 0.004)
0.25 ± 0.15
(0.010± 0.006)
0.25 ± 0.15
(0.010 ± 0.006)
PAD LAYOUT
DIMENSIONS
P
W
1.60 ± 0.20
(0.063 ± 0.008)
2.03 ± 0.20
(0.080 ± 0.008)
3.20 ± 0.20
(0.126 ± 0.008)
L
0.82 ± 0.10
(0.032 ± 0.006
1.27 ± 0.20
(0.050 ± 0.008)
1.60 ± 0.20
(0.063 ± 0.008)
BW
0.25 ± 0.10
(0.010 ± 0.004)
0.30 ± 0.10
(0.012 ± 0.004)
0.50 ± 0.10
(0.020 ± 0.004)
SIZE
A
0.38
0.64
0.89
B
0.89
1.27
1.65
C
1.27
1.91
2.54
D
0.20
0.28
0.45
E
0.40
0.50
0.80
0.40 ± 0.05
(0.015 ± 0.002)
0.50 ± 0.05
(0.020 ± 0.002)
0.80 ± 0.10
(0.031 ± 0.004)
0306
(0.015) (0.035) (0.050) (0.008) (0.015)
0508
(0.025) (0.050) (0.075) (0.011) (0.020)
0612
(0.035) (0.065) (0.010) (0.018) (0.031)
73
IDC Low Inductance Capacitors (SnPb)
0306/0612/0508 IDC with Sn/Pb Termination
GENERAL DESCRIPTION
Inter-Digitated Capacitors (IDCs) are used for both semiconductor
package and board level decoupling. The equivalent series
inductance (ESL) of a single capacitor or an array of capacitors in
parallel determines the response time of a Power Delivery Network
(PDN). The lower the ESL of a PDN, the faster the response time.
A designer can use many standard MLCCs in parallel to reduce
ESL or a low ESL Inter-Digitated Capacitor (IDC) device. These IDC
devices are available in versions with a maximum height of 0.95mm
or 0.55mm.
IDCs are typically used on packages of semiconductor products
with power levels of 15 watts or greater. Inter-Digitated Capacitors
are used on CPU, GPU, ASIC, and ASSP devices produced on
0.13μ, 90nm, 65nm, and 45nm processes. IDC devices are used
on both ceramic and organic package substrates. These low ESL
surface mount capacitors can be placed on the bottom side or the
top side of a package substrate. The low profile 0.55mm maximum
height IDCs can easily be used on the bottom side of BGA
packages or on the die side of packages under a heat spreader.
IDCs are used for board level decoupling of systems with speeds of
300MHz or greater. Low ESL IDCs free up valuable board space by
reducing the number of capacitors required versus standard
MLCCs. There are additional benefits to reducing the number of
capacitors beyond saving board space including higher reliability
from a reduction in the number of components and lower
placement costs based on the need for fewer capacitors.
The Inter-Digitated Capacitor (IDC) technology was developed by
AVX. This is the second family of Low Inductance MLCC products
created by AVX. IDCs are a cost effective alternative to AVX’s first
generation low ESL family for high-reliability applications known as
LICA (Low Inductance Chip Array).
AVX IDC products are available with a lead termination for high
reliability military and aerospace applications that must avoid tin
whisker reliability issues.
0612
+
–
+
–
0508
0306
TYPICAL IMPEDANCE
10
Impedance (Ohms)
MLCC_1206
1
LICC_0612
0.1
IDC_0612
0.01
0.001
1
10
100
1000
Frequency (MHz)
Not RoHS Compliant
HOW TO ORDER
L
Style
3
L
1
6
D
225
M
A
B
3
A
Thickness
Max. Thickness
mm (in.)
Voltage Dielectric Capacitance Capacitance Failure Termination Packaging
Tolerance Rate
B = 5% min.
C = X7R
Code (In pF)
Available
4 = 4V
2 Sig. Digits + M = ±20% A = N/A
Lead
1=7" Reel
6 = 6.3V D = X5R
Number of
3=13" Reel
Z = 10V Z = X7S
Zeros
Y = 16V
3 = 25V
NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers.
IDC
Low
Number
Case
Inductance
of
Size
Terminals
2 = 0508
1 = 8 Terminals
3 = 0612
4 = 0306
A=Standard
S=0.55 (0.022)
PERFORMANCE CHARACTERISTICS
Capacitance Tolerance
Operation
Temperature Range
Temperature Coefficient
Voltage Ratings
Dissipation Factor
±20% Preferred
X7R = -55°C to +125°C
X5R = -55°C to +85°C
X7S = -55°C to +125°C
±15% (0VDC), ±22% (X7S)
4, 6.3, 10, 16, 25 VDC
≤ 6.3V = 6.5% max;
10V = 5.0% max;
≥ 16V = 3.5% max
100,000MΩ min, or 1,000MΩ per
μF min.,whichever is less
Dielectric Strength
CTE (ppm/C)
Terminations
Available
No problems observed after 2.5 x RVDC
for 5 seconds at 50mA max current
12.0
Thermal Conductivity
4-5W/M K
Plated Nickel and Solder
Insulation Resistance
(@+25°C, RVDC)
74
+
–
+
–
IDC Low Inductance Capacitors (SnPb)
0306/0612/0508 IDC with Sn/Pb Termination
SIZE
Max.
mm
Thickness (in.)
WVDC
Cap
(μF)
0.010
0.022
0.033
0.047
0.068
0.10
0.22
0.33
0.47
0.68
1.0
1.5
2.2
3.3
4
0306
0.55
(0.022)
6.3
4
Thin 0508
0.55.
(0.022)
6.3
10
16
25
4
0508
0.95
(0.037)
6.3
10
16
25
4
Thin 0612
0.55
(0.022)
6.3 10
16
4
0612
0.95
(0.037)
6.3
10
16
25
4
THICK 0612
1.22
(0.048)
6.3
10
16
PHYSICAL DIMENSIONS AND PAD LAYOUT
W
Consult factory for
additional requirements
= X7R
= X5R
= X7S
T
D
E
P
BW
A
B
C
BL
L
PHYSICAL CHIP DIMENSIONS
SIZE
0306
0508
0612
millimeters (inches)
BL
0.20 ± 0.10
(0.008± 0.004)
0.25 ± 0.15
(0.010± 0.006)
0.25 ± 0.15
(0.010 ± 0.006)
PAD LAYOUT
DIMENSIONS
P
W
1.60 ± 0.20
(0.063 ± 0.008)
2.03 ± 0.20
(0.080 ± 0.008)
3.20 ± 0.20
(0.126 ± 0.008)
L
0.82 ± 0.10
(0.032 ± 0.006
1.27 ± 0.20
(0.050 ± 0.008)
1.60 ± 0.20
(0.063 ± 0.008)
BW
0.25 ± 0.10
(0.010 ± 0.004)
0.30 ± 0.10
(0.012 ± 0.004)
0.50 ± 0.10
(0.020 ± 0.004)
SIZE
A
0.38
0.64
0.89
B
0.89
1.27
1.65
C
1.27
1.91
2.54
D
0.20
0.28
0.45
E
0.40
0.50
0.80
0.40 ± 0.05
(0.015 ± 0.002)
0.50 ± 0.05
(0.020 ± 0.002)
0.80 ± 0.10
(0.031 ± 0.004)
0306
(0.015) (0.035) (0.050) (0.008) (0.015)
0508
(0.025) (0.050) (0.075) (0.011) (0.020)
0612
(0.035) (0.065) (0.010) (0.018) (0.031)
75
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