DDR SDRAM 128Mb F-die (x4, x8)
DDR SDRAM
128Mb F-die DDR SDRAM Specification
Revision 1.1
May 2004
Rev. 1.1 May. 2004
DDR SDRAM 128Mb F-die (x4, x8)
128Mb F-die Revision History
Revision 0.0 (January, 2004)
- Target spec. release
Revision 0.1 (February, 2004)
- Modified DC current spec.
Revision 1.0 (March, 2004)
- Revision 1.0 spec. release.
Revision 1.1 (May, 2004)
- Corrected typo.
DDR SDRAM
Rev. 1.1 May. 2004
DDR SDRAM 128Mb F-die (x4, x8)
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
DDR SDRAM
Ordering Information
Part No.
K4H280438F-TC/LA2
K4H280438F-TC/LB0
K4H280438F-TC/LA0
K4H280838F-TC/LB3
K4H280838F-TC/LA2
K4H280838F-TC/LB0
16M x 8
32M x 4
Org.
Max Freq.
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
66pin TSOP II
SSTL2
66pin TSOP II
Interface
Package
Operating Frequencies
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
*CL : CAS Latency
133MHz
166MHz
A2(DDR266@CL=2.0)
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
133MHz
A0(DDR200@CL=2.0)
100MHz
-
Rev. 1.1 May. 2004
DDR SDRAM 128Mb F-die (x4, x8)
Pin Description
DDR SDRAM
16Mx8
32Mx4
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
Bank Address
BA0~BA1
Auto Precharge
A10
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
128Mb Package Pinout
Organization
32Mx4
16Mx8
Row Address
A0~A11
A0~A11
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 May. 2004
DDR SDRAM 128Mb F-die (x4, x8)
Package Physical Dimension
DDR SDRAM
Units : Millimeters
(0.80)
(0.50)
(10×)
(10×)
0.125
+0.075
-0.035
(0.50)
0×~8×
(R
0.2
5
)
#66
#34
10.16±0.10
(1.50)
#1
(1.50)
#33
0.665±0.05
0.210±0.05
(0.80)
0.
15
)
0.05 MIN
(0.71)
0.65TYP
0.65±0.08
0.30±0.08
(10×)
0.10 MAX
[
0.075 MAX ]
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
(R
66pin TSOPII / Package dimension
Rev. 1.1 May. 2004
(R
0.
25
)
(4
×
)
(R
0.1
5)
(10×)
1.20MAX
22.22±0.10
1.00±0.10
0.25TYP
0.45~0.75
11.76±0.20
(10.16)
51mcu
京公网安备 11010802033920号
EEWORLD
