28C64AFT-15P datasheet, PDF - EEWORLD Datasheet

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28C64AFT-15P: Description64K (8K x 8) CMOS EEPROM; File Size67KB，8 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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28C64AFT-15P Overview

64K (8K x 8) CMOS EEPROM

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28C64A

64K (8K x 8) CMOS EEPROM

FEATURES

• Fast Read Access Time—150 ns

• CMOS Technology for Low Power Dissipation

- 30 mA Active

- 100

A Standby

• Fast Byte Write Time—200

s or 1 ms

• Data Retention >200 years

• High Endurance - Minimum 100,000 Erase/Write

Cycles

• Automatic Write Operation

- Internal Control Timer

- Auto-Clear Before Write Operation

- On-Chip Address and Data Latches

• Data Polling

• Ready/Busy

• Chip Clear Operation

• Enhanced Data Protection

- V

Detector

- Pulse Filter

- Write Inhibit

• Electronic Signature for Device Identiﬁcation

• 5-Volt-Only Operation

• Organized 8Kx8 JEDEC Standard Pinout

- 28-pin Dual-In-Line Package

- 32-pin PLCC Package

- 28-pin Thin Small Outline Package (TSOP)

8x20mm

- 28-pin Very Small Outline Package (VSOP)

8x13.4mm

• Available for Extended Temperature Ranges:

- Commercial: 0˚C to +70˚C

PACKAGE TYPES

RDY/BSY

A12

I/O0

I/O1

I/O2

•1

Vcc

A11 A4

A10 A2

I/O7

I/O6

I/O0

I/O5

I/O4

I/O3

RDY/BSY

A12

Vcc

A11

A10

I/O7

I/O6

• Pin 1 indicator on PLCC on top of package

A11

Vcc

RDY/BSY

A12

A11

RDY/BSY

A12

I/O1

I/O2

Vss

I/O3

I/O4

I/O5

DIP/SOIC

PLCC

A10

I/07

I/06

I/05

I/04

I/03

Vss

I/02

I/01

I/00

A10

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

TSOP

VSOP

DESCRIPTION

The Microchip Technology Inc. 28C64A is a CMOS 64K non-

volatile electrically Erasable PROM. The 28C64A is

accessed like a static RAM for the read or write cycles without

the need of external components. During a “byte write”, the

address and data are latched internally, freeing the micropro-

cessor address and data bus for other operations. Following

the initiation of write cycle, the device will go to a busy state

and automatically clear and write the latched data using an

internal control timer. To determine when the write cycle is

complete, the user has a choice of monitoring the Ready/

Busy output or using Data polling. The Ready/Busy pin is an

open drain output, which allows easy conﬁguration in wired-

or systems. Alternatively, Data polling allows the user to read

the location last written to when the write operation is com-

plete. CMOS design and processing enables this part to be

used in systems where reduced power consumption and reli-

ability are required. A complete family of packages is offered

to provide the utmost ﬂexibility in applications

BLOCK DIAGRAM

I/O0

I/O7

Rdy/

Busy

Data Protection

Circuitry

Chip Enable/

Output Enable

Control Logic

Auto Erase/Write

Timing

Data

Poll

Input/Output

Buffers

Program Voltage

Generation

A12

Decoder

Y Gating

Decoder

16K bit

Cell Matrix

1996 Microchip Technology Inc.

DS11109H-page 1

This document was created with FrameMaker 4 0 4

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