28LV011
3.3V 1 Megabit (128K x 8-Bit)
EEPROM
V
CC
V
SS
RES
OE
CE
WE
RES
I/O Buffer and
Input Latch
Control Logic Timing
High Voltage
Generator
I/O0
I/O7
RDY/Busy
28LV011
A0
A6
Address
Buffer and
Latch
A7
A16
Y Decoder
Y Gating
X Decoder
Memory Array
Data Latch
Logic Diagram
Memory
F
EATURES
:
• 3.3V low voltage operation 128K x 8 Bit EEPROM
• R
AD
-P
AK
® radiation-hardened against natural space
radiation
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
- SEL
TH
> 84 MeV/mg/cm
2
- SEU
TH
> 37 Mev/mg/cm
2
(read mode)
- SEU saturated cross section = 3E-6 cm
2
(read mode)
- SEU
TH
= 11.4 Mev/mg/cm
2
(write mode)
- SEU saturated cross section = 5E-3 cm
2
(write mode)
with hard errors
• Package:
- 32 Pin R
AD
-P
AK
® flat pack
- 32 Pin R
AD
-P
AK
® DIP
- JEDEC-approved byte-wide pinout
• Address Access Time:
- 200, 250 ns Access times available
• High endurance:
- 10,000 erase/write (in Page Mode), 10-year data
retention
• Page write mode:
- 1 to 128 bytes
• Automatic programming
- 15 ms automatic page/byte write
• Low power dissipation
- 20 mW/MHz active current (typ.)
- 72 µ W standby (maximum)
D
ESCRIPTION
:
Maxwell Technologies’ 28LV011 high density, 3.3V, 1 Megabit
EEPROM microcircuit features a greater than 100 krad (Si)
total dose tolerance, depending upon space mission. The
28LV011 is capable of in-system electrical Byte and Page pro-
grammability. It has a 128-Byte Page Programming function to
make its erase and write operations faster. It also features
Data Polling and a Ready/Busy signal to indicate the comple-
tion of erase and programming operations. In the 28LV011,
hardware data protection is provided with the RES pin, in addi-
tion to noise protection on the WE signal and write inhibit on
power on and off. Meanwhile, software data protection is
implemented using the JEDEC-optional Standard algorithm.
The 28LV011 is designed for high reliability in the most
demanding space applications.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
® provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
Note:The recommended form of data protection during power
on/off is to hold the RES pin to V
SS
during power up and power
down. This may be accompanied by connecting the RES pin
to the CPU reset line. Failure to provide adequate protection
during power on/off may result in lost or modified data.
05.28.02 Rev 2
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301- www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
3.3V 1 Megabit (128K x 8-Bit) EEPROM
T
ABLE
1. 28LV011A P
INOUT
D
ESCRIPTION
P
IN
S
YMBOL
D
ESCRIPTION
Address
Input/Output
Output Enable
Chip Enable
Write Enable
Power Supply
Ground
Ready/Busy
Reset
12-5, 27, 26, 23, 25, A0-A16
4, 28, 3, 31, 2
13-15, 17-21
24
22
29
32
16
1
30
I/O0 - I/O7
OE
CE
WE
V
CC
V
SS
RDY/BUSY
RES
28LV011
Memory
T
ABLE
2. 28LV011 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Supply Voltage (Relative to Vss)
Input Voltage (Relative to Vss)
Operating Temperature Range
Storage Temperature Range
1. V
IN
min = -3.0 V for pulse width < 50 ns.
S
YMBOL
V
CC
V
IN
T
OPR
T
STG
M
IN
-0.6
-0.5
1
-55
-65
M
AX
7.0
7.0
125
150
U
NIT
V
V
°C
°C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC
1
I
CC
2
I
CC
3A
I
CC
3B
V
ARIATION
±10%
±10%
±10%
±10%
05.28.02 Rev 2
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
3.3V 1 Megabit (128K x 8-Bit) EEPROM
T
ABLE
4. 28LV011 R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
Input Voltage
RES_PIN
Operating Temperature Range
1. V
IL
min = -1.0 V for pulse width < 50 ns.
2. V
IH
min = 2.2 V for V
CC
= 3.6 V.
SYMBOL
V
CC
V
IL
V
IH
V
H
T
OPR
MIN
3.0
-0.3
1
2.0
2
V
CC
-0.5
-55
28LV011
MAX
3.6
0.8
V
CC
+0.3
V
CC
+1
+125
UNIT
V
V
°C
T
ABLE
5. 28LV011 C
APACITANCE
(T
A
= 25°C, F = 1MH
Z
)
P
ARAMETER
Input Capacitance: V
IN
= 0V
1
Output Capacitance: V
OUT
= 0V
1
1. Guaranteed by design.
S
YMBOL
C
IN
C
OUT
M
IN
--
--
M
AX
6
12
U
NIT
pF
pF
Memory
T
ABLE
6. 28LV011 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V ± 0.3, T
A
= -55
TO
+125°C
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Leakage Current
Output Leakage Cur-
rent
Standby V
CC
Current
Operating V
CC
Current
T
EST
C
ONDITIONS
V
CC
= 3.6V, V
IN
= 3.6V
V
CC
= 3.6V, V
OUT
= 3.6V/0.4V
CE = V
CC
CE = V
IH
I
OUT
= 0mA, Duty = 100%, Cycle = 1 µ s
@ V
CC
= 3.3V
I
OUT
= 0mA, Duty = 100%, Cycle = 250 ns @ V
CC
=
3.3V
S
UBGROUPS
S
YMBOL
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
I
LI
I
LO
I
CC1
I
CC2
I
CC3
M
IN
--
--
--
--
--
--
1, 2, 3
V
IL
V
IH
V
H
V
OL
V
OH
--
2.0
1
V
CC
-0.5
--
V
CC
x0.8
M
AX
2
2
20
1
6
15
0.8
--
--
0.4
--
V
U
NIT
µA
µA
µA
mA
mA
Input Voltage
Output Voltage
I
OL
= 2.1 mA
I
OH
= -400 µ A
1, 2, 3
V
1. V
IH
min = 2.2V for V
CC
= 3.6V.
05.28.02 Rev 2
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
3.3V 1 Megabit (128K x 8-Bit) EEPROM
T
ABLE
7. 28LV011 AC C
HARACTERISTICS FOR
R
EAD
O
PERATION1
(V
CC
= 3.3V ± 10%, T
A
= -55
TO
+125 °C
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Functional Test
Address Access Time
-200
-250
Chip Enable Access Time
-200
-250
Output Enable Access Time
-200
-250
Output Hold to Address Change
-200
-250
Output Disable to High-Z
2
-200
-250
Output Disable to High-Z
-200
-250
RES to Output Delay
3
-200
-250
T
EST
C
ONDITIONS
Verify Truth Table
CE = OE = V
IL
, WE = V
IH
S
UBGROUPS
7, 8A, 8B
9, 10, 11
S
YMBOL
All
t
ACC
--
--
OE = V
IL
, WE = V
IH
9, 10, 11
t
CE
--
--
CE = V
IL
, WE = V
IH
9, 10, 11
t
OE
0
0
CE = OE = V
IL
, WE = V
IH
9, 10, 11
t
OH
0
0
CE = V
IL
, WE = V
IH
CE = OE = V
IL
, WE = V
IH
CE = V
IL
, WE = V
IH
CE = OE = V
IL
, WE = V
IH
CE = OE = V
IL
WE = V
IH
9, 10, 11
t
DF
0
0
9, 10, 11
t
DFR
0
0
9, 10, 11
t
RR
0
0
M
IN
28LV011
M
AX
U
NIT
ns
200
250
ns
200
250
ns
110
120
ns
--
--
ns
50
50
ns
300
350
ns
525
550
Memory
1. Test conditions: Input pulse levels - 0.4V to 2.4V; input rise and fall times < 20 ns; output load - 1 TTL gate + 100 pF (including
scope and jig); reference levels for measuring timing - 0.8V/1.8V.
2.
t
DF
and t
DFR
is defined as the time at which the output becomes an open circuit and data is no longer driven.
3. Guaranteed by design.
05.28.02 Rev 2
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
3.3V 1 Megabit (128K x 8-Bit) EEPROM
28LV011
T
ABLE
8. 28LV011 AC E
LECTRICAL
C
HARACTERISTICS FOR
E
RASE AND
W
RITE
O
PERATIONS
(V
CC
= 3.3V ± 10%, T
A
= -55
TO
+125 °C
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Address Setup Time
-200
-250
Chip Enable to Write Setup Time (WE controlled)
-200
-250
Write Pulse Width (CE controlled)
-200
-250
Write Pulse Width (WE controlled)
-200
-250
Address Hold Time
-200
-250
Data Setup Time
-200
-250
Data Hold Time
-200
-250
Chip Enable Hold Time (WE controlled)
-200
-250
Write Enable to Write Setup Time (CE controlled)
-200
-250
Write Enable Hold Time (CE controlled)
-200
-250
Output Enable to Write Setup Tim
-200
-250
Output Enable Hold Time
-200
-250
Write Cycle Time
1,2
-200
-250
S
UBGROUPS
9, 10, 11
S
YMBOL
t
AS
0
0
9, 10, 11
t
CS
0
0
9, 10, 11
t
CW
200
250
9, 10, 11
t
WP
200
250
9, 10, 11
t
AH
125
150
9, 10, 11
t
DS
100
100
9, 10, 11
t
DH
10
10
9, 10, 11
t
CH
0
0
9, 10, 11
t
WS
0
0
9, 10, 11
t
WH
0
0
9, 10, 11
t
OES
0
0
9, 10, 11
t
OEH
0
0
9, 10, 11
t
WC
--
--
15
15
--
--
ms
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
M
IN
M
AX
U
NIT
ns
Memory
05.28.02 Rev 2
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
Embedded System
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