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BU-65171P6-202

Description
Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CPGA70, PGA-70
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size358KB,46 Pages
ManufacturerData Device Corporation
Download Datasheet Parametric View All

BU-65171P6-202 Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CPGA70, PGA-70

BU-65171P6-202 Parametric

Parameter NameAttribute value
Parts packaging codePGA
package instructionPGA, PGA70(UNSPEC)
Contacts70
Reach Compliance Codecompliant
Is SamacsysN
Address bus width16
boundary scanNO
letter of agreementMIL-STD-1553A; MIL-STD-1553B; MCAIR; STANAG-3838
Data encoding/decoding methodsBIPH-LEVEL(MANCHESTER)
Maximum data transfer rate0.125 MBps
External data bus width16
JESD-30 codeR-CPGA-P70
length48.26 mm
low power modeYES
Number of serial I/Os2
Number of terminals70
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA70(UNSPEC)
Package shapeRECTANGULAR
Package formGRID ARRAY
power supply5 V
Certification statusNot Qualified
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width25.4 mm
uPs/uCs/peripheral integrated circuit typeSERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches1
BU-65170/61580 AND BU-61585
MIL-STD-1553A/B NOTICE 2 RT
AND BC/RT/MT, ADVANCED
COMMUNICATION ENGINE (ACE)
Make sure the next
Card you purchase
has...
®
FEATURES
Fully Integrated MIL-STD-1553
Interface Terminal
Flexible Processor/Memory Interface
Standard 4K x 16 RAM and Optional
12K x 16 or 8K x 17 RAM Available
Optional RAM Parity Generation/
Checking
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Flexible RT Data Buffering
Programmable
I
llegalization
DESCRIPTION
DDC's BU-65170, BU-61580 and BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal (BC/RT/MT) Advanced Communication
Engine (ACE) terminals comprise a complete integrated interface
between a host processor and a MIL-STD-1553 A and B or STANAG
3838 bus.
The ACE series is packaged in a 1.9 -square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM) ceramic package that is well suited
for applications with stringent height requirements.
The BU-61585 ACE integrates dual transceiver, protocol, memory
management, processor interface logic, and a total of 12K words of
RAM in a choice of DIP or flat pack packages. The BU-61585 requires
+5 V power and either -15 V or -12 V power.
The BU-61585 internal RAM can be configured as 12K x 16 or 8K x
17. The 8K x 17 RAM feature provides capability for memory integri-
ty checking by implementing RAM parity generation and verification
on all accesses. To minimize board space and “glue” logic, the ACE
provides ultimate flexibility in interfacing to a host processor and inter-
nal/external RAM.
The advanced functional architecture of the ACE terminals provides
software compatibility to DDC's Advanced Integrated Multiplexer
(AIM) series hybrids, while incorporating a multiplicity of architectural
enhancements. It allows flexible operation while off-loading the host
processor, ensuring data sample consistency, and supports bulk data
transfers.The ACE hybrids may be operated at either 12 or 16 MHz.
Wire bond options allow for programmable RT address (hardwired is
standard) and external transmitter inhibit inputs.
Selective Message Monitor
Simultaneous RT/Monitor Mode
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1992, 1999 Data Device Corporation
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