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NCC5003MAGWP

Description
BUSSED RESISTOR NETWORK
File Size42KB,1 Pages
ManufacturerCALMIRCO
Websitehttp://www.calmicro.com/
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NCC5003MAGWP Overview

BUSSED RESISTOR NETWORK

CALIFORNIA MICRO DEVICES
NCC
BUSSED RESISTOR NETWORK
California Micro Devices’ resistor arrays are the hybrid
equivalent to the bussed resistor networks available in
surface-mount packages. The resistors are spaced on
ten mil centers resulting in reduced real estate. These
chips are manufactured using advanced thin film
processing techniques and are 100% electrically
tested and visually inspected.
STANDARD NETWORK SCHEMATIC DIAGRAM
90
Formats
R1
R2
R3
R4
R5
R6
R7
R8
60
Die Size: 90±3 x 60±3 mils
Bonding Pads: 5x7 mils typical
ELECTRICAL SPECIFICATIONS
Parameter
TCR
Operating Voltage
Power Rating (per resistor)
Thermal Shock
High Temperature Exposure
Moisture
Life
Noise
Short Time Overload
Insulation Resistance
–55°C to 125°C
–55°C to 125°C
@ 70°C (Derate linearly to 0@150°C)
Method 107 MIL-STD-202F
100Hrs @ 150°C Ambient
Method 106 MIL-STD-202F
Method 108 MIL-STD-202F (125°C/1000hr)
Method 308 MIL-STD-202F
250k
MIL-R-83401
@25°C
Test Conditions
±100ppm/C
50Vdc
50mw
±0.25%@
∆R
±0.25%
∆R
±0.5%
∆R
±0.5%
∆R
–35dB
–30dB
0.25%
1 x 10
1 2
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Min.
M E C H A N I C A L S P E C I F I C AT I O N S
Substrate
Isolation Layer
Backing
Metalization
Passivation
Silicon 10 ±2 mils thick
Si02 10,000Å thick, min
Lapped (gold optional)
Aluminum 10,000Å thick, min
(15,000Å gold optional)
Silicon Nitride
VA L U E S
8 resistors from 100
to 500K
PA C K AG I N G
Two inch square trays of 196 chips maximum is standard.
N OT E S
1. Resistor pattern may vary from one value to another.
PA R T N U M B E R D E S I G N AT I O N
NCC
Series
5003
Value
First 3 digits are
significant value.
Last digit repres-
sents number of
zeros. R indicates
decimal point.
F
Tolerance
D = ±0.5%
F = ±1%
G = ±2%
J = ±5%
K = ±10%
M = ±20%
C0970500
A
TCR
No Letter = ±100ppm
A = ±50ppm
B = ±25ppm
G
Bond Pads
G = Gold
No Letter = Aluminum
W
Backing
W = Gold
L = Lapped
No Letter = Either
P
Ratio
Tolerance
No Letter = 1%
P = 0.5%
© 2000 California Micro Devices Corp. All rights reserved.
6/2/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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