NB6L16
2.5 V / 3.3 V Multilevel
Input to Differential
LVPECL/LVNECL
Clock or Data Receiver/
Driver/Translator Buffer
Description
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The NB6L16 is a high precision, low power ECL differential clock
or data receiver/driver/translator buffer. The device is functionally
equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With
output transition times of 70 ps, it is ideally suited for high frequency,
low power systems. The device is targeted for Backplane buffering,
GbE clock/data distribution, Fibre Channel distribution and SONET
clock/data distribution applications.
Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV
ECL signals.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
8
1
SOIC−8 NB
D SUFFIX
CASE 751−07
8
1
TSSOP−8
DT SUFFIX
CASE 948R−02
MARKING DIAGRAMS*
8
6L16
ALYW
G
1
SOIC−8 NB
A
L
Y
W
G
1
TSSOP−8
8
6L16
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
Input Clock Frequency
≥
6 GHz
Input Data Rate Frequency
≥
6 Gb/s
Low 12 mA Typical Power Supply Current
70 ps Typical Rise/Fall Times
130 ps Input Propagation Delay
On-Chip Reference for ECL Single-Ended Input
−
V
BB
Output
PECL Mode Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
−2.375
V to
−3.465
V
Open Input Default State
LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input
Compatible
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note
AND8002/D.
ORDERING INFORMATION
Device
NB6L16DG
NB6L16DR2G
NB6L16DTG
NB6L16DTR2G
Package
SOIC−8 NB
(Pb-Free)
SOIC−8 NB
(Pb-Free)
TSSOP−8
(Pb-Free)
TSSOP−8
(Pb-Free)
Shipping†
98 Units / Tube
2500 Tape & Reel
100 Units / Tube
2500 Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
August, 2016
−
Rev. 9
1
Publication Order Number:
NB6L16/D
NB6L16
V
CC
NC
1
R2
R1
8
D
2
7
Q
D
3
R1
R2
6
Q
V
BB
4
5
V
EE
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
1
2
Name
NC
D
I/O
−
LVDS, CML, LVPECL,
LVNECL, LVTTL, LVCMOS
Input
LVDS, CML, LVPECL,
LVNECL, LVTTL, LVCMOS
Input
−
−
ECL Output
ECL Output
−
−
Default State
−
LOW
Description
No Connect. The NC pin is electrically connected to the die and MUST
be left open.
Non-inverted differential clock/data input. Internal 75 kW to V
CC
and
37.5 kW to V
EE
.
Inverted differential clock/data input. Internal 37.5 kW to V
CC
and 75 kW
to V
EE
.
Internally generated ECL reference voltage supply.
Negative power supply voltage.
Inverted differential ECL output. Typically terminated with 50
W
resistor
to V
CC
– 2.0 V.
Non-inverted differential ECL output. Typically terminated with 50
W
resistor to V
CC
– 2.0 V.
Positive power supply voltage.
3
D
HIGH
4
5
6
7
8
V
BB
V
EE
Q
Q
V
CC
−
−
Table 2. ATTRIBUTES
Characteristics
Internal Input Default State Resistor
Internal Input Default State Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8 NB
TSSOP−8
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note
AND8003/D.
Oxygen Index: 28 to 34
(R1)
(R2)
Value
37.5 kW
75 kW
> 2 kV
> 100 V
> 1 kV
Pb-Free Pkg
Level 1
Level 3
UL 94 V−0 @ 1.125 in
167
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2
NB6L16
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
V
INPP
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Differential Input Voltage
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder
Standard
Pb-Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
v
3 sec @ 248°C
v
3 sec @ 260°C
SOIC−8 NB
SOIC−8 NB
SOIC−8 NB
TSSOP−8
TSSOP−8
TSSOP−8
|D
−
D|
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
CC
−
V
EE
≥
2.8 V
V
CC
−
V
EE
<
2.8 V
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
25
50
2.8
|V
CC
−
V
EE
|
±0.5
−40
to +85
−65
to +150
190
130
41 to 44
185
140
41 to 44
265
265
Un-
its
V
V
V
mA
V
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NB6L16
Table 4. DC CHARACTERISTICS, PECL
(V
CC
= 2.5 V, V
EE
= 0 V (Note 3))
−40°C
Symbol
I
EE
V
OH
V
OL
Characteristic
Negative Power Supply Current (Note 4)
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Min
10
1350
565
Typ
12
1450
725
Max
18
1550
870
Min
10
1400
630
25°C
Typ
12
1500
765
Max
18
1600
920
Min
10
1450
690
85°C
Typ
12
1550
825
Max
18
1650
970
Unit
mA
mV
mV
DIFFERENTIAL INPUT DRIVEN Single-Ended
((Figures 10, 12) (Note 7))
V
th
V
IH
V
IL
Input Threshold Reference Voltage
Range (Notes 1, 6)
Single-Ended Input HIGH Voltage
Single-Ended Input LOW Voltage
1125
V
th
+75
V
EE
V
CC
−75
V
CC
V
th
−75
1125
V
th
+75
V
EE
V
CC
−75
V
CC
V
th
−75
1125
V
th
+75
V
EE
V
CC
−75
V
CC
V
th
−75
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
((Figures 11, 13) (Note 8))
V
IHD
V
ILD
V
CMR
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range
(Differential Cross-Point Voltage)
(Note 2)
Differential Input Voltage (V
IHD
−
V
ILD
)
Input HIGH Current
D
D
Input LOW Current
D
D
−150
−150
1200
V
EE
950
V
CC
V
CC
−75
V
CC
−38
2500
50
10
−5
−30
150
150
−150
−150
1200
V
EE
950
V
CC
V
CC
−75
V
CC
−38
2500
50
10
−5
−30
150
150
−150
−150
1200
V
EE
950
V
CC
V
CC
−75
V
CC
−38
2500
50
10
−5
−30
150
150
mV
mV
mV
V
ID
I
IH
75
75
75
mV
mA
I
IL
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. V
th
is applied to the complementary input when operating in Single-Ended mode.
2. V
CMR
minimum varies 1:1 with V
EE
, V
CMR
maximum varies 1:1 with V
CC
.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to
−1.3
V.
4. All input and output pins left open.
5. All loading with 50
W
to V
CC
−
2.0 V.
6. Do not use V
BB
as a reference voltage for Single-Ended PECL signals when operating device at V
CC
−
V
EE
< 3.0 V.
7. V
th
, V
IH
, and V
IL
parameters must be complied with simultaneously.
8. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
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NB6L16
Table 5. DC CHARACTERISTICS, PECL
(V
CC
= 3.3 V, V
EE
= 0 V (Note 3))
Symbol
I
EE
V
OH
V
OL
Characteristic
Negative Power Supply Current (Note 4)
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Min
10
2150
1365
−40°C
Typ
12
2250
1525
Max
18
2350
1670
Min
10
2200
1430
25°C
Typ
12
2300
1565
Max
18
2400
1720
Min
10
2250
1490
85°C
Typ
12
2350
1625
Max
18
2450
1770
Unit
mA
mV
mV
DIFFERENTIAL INPUT DRIVEN Single-Ended
((Figures 10, 12) (Note 6))
V
th
V
IH
V
IL
V
BB
Input Threshold Reference Voltage
Range (Note 1)
Single-Ended Input HIGH Voltage
Single-Ended Input LOW Voltage
Output Voltage Reference
1125
V
th
+75
V
EE
1880
1980
V
CC
−75
V
CC
V
th
−75
2070
1125
V
th
+75
V
EE
1880
1980
V
CC
−75
V
CC
V
th
−75
2070
1125
V
th
+75
V
EE
1880
1980
V
CC
−75
V
CC
V
th
−75
2070
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
((Figures 11, 13) (Note 7))
V
IHD
V
ILD
V
CMR
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 2)
Differential Input Voltage (V
IHD
−
V
ILD
)
Input HIGH Current
D
D
Input LOW Current
D
D
−150
−150
1200
V
EE
950
V
CC
V
CC
−75
V
CC
−38
2500
50
10
−5
−30
150
150
−150
−150
1200
V
EE
950
V
CC
V
CC
−75
V
CC
−38
2500
50
10
−5
−30
150
150
−150
−150
1200
V
EE
950
V
CC
V
CC
−75
V
CC
−38
2500
50
10
−5
−30
150
150
mV
mV
mV
V
ID
I
IH
75
75
75
mV
mA
I
IL
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. V
th
is applied to the complementary input when operating in Single-Ended mode.
2. V
CMR
minimum varies 1:1 with V
EE
, V
CMR
maximum varies 1:1 with V
CC
.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to
−0.5
V.
4. All input and output pins left open.
5. All loading with 50
W
to V
CC
−
2.0 V.
6. V
th
, V
IH
, and V
IL
parameters must be complied with simultaneously.
7. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
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