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NAND01GR3M2AZB5F

Description
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP
Categorystorage    storage   
File Size170KB,23 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
Download Datasheet Parametric View All

NAND01GR3M2AZB5F Overview

256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP

NAND01GR3M2AZB5F Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Reach Compliance Codeunknow
ECCN codeEAR99
JESD-30 codeR-PBGA-B137
Memory IC TypeMEMORY CIRCUIT
Mixed memory typesFLASH+SDRAM
Number of terminals137
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA137,10X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
power supply1.8 V
Certification statusNot Qualified
Nominal supply voltage (Vsup)1.8 V
surface mountYES
Temperature levelOTHER
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
NAND256-M
NAND512-M, NAND01G-M
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND
Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP
Features
Multi-Chip Packages
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND
Flash + 1 die of 256 Mb (x16) SDR
LPSDRAM
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND
Flash + 2 dice of 256 Mb (x16) SDR
LPSDRAMs
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND
Flash +1 die of 256 Mb (x16) DDR
LPSDRAM
– 1 die of 512 Mb (x16) NAND Flash + 1 die
of 256 Mb or 512 Mb (x16) DDR LPSDRAM
Supply voltages
– V
DDF
= 1.7V to 1.95V or 2.5V to 3.6V
– V
DDD
= V
DDQD
= 1.7V to 1.9V
Electronic Signature
ECOPACK
®
packages
Temperature range
– -30 to 85°C
FBGA
TFBGA107 10.5 x 13 x 1.2mm
TFBGA149 10 x 13.5 x 1.2mm
LFBGA137 10.5 x 13 x 1.4mm
TFBGA137 10.5 x 13 x 1.2 mm
(1)
(1) Preliminary specifications.
Fast Block Erase
– Block erase time: 2ms (typ)
Status Register
Data integrity
– 100,000 Program/Erase cycles
– 10 years Data Retention
Flash Memory
NAND Interface
– x8 or x16 bus width
– Multiplexed Address/ Data
Page size
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
Block size
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
Page Read/Program
– Random access: 15µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
Copy Back Program mode
– Fast page copy without external buffering
LPSDRAM
Interface: x16 or x 32 bus width
Deep Power Down mode
1.8v LVCMOS interface
Quad internal Banks controlled by BA0 and
BA1
Automatic and controlled Precharge
Auto Refresh and Self Refresh
– 8,192 Refresh cycles/64ms
– Programmable Partial Array Self Refresh
– Auto Temperature Compensated Self
Refresh
Wrap sequence: sequential/interleave
Burst Termination by Burst Stop command and
Precharge command
August 2006
Rev 5
1/23
www.st.com
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