EEWORLDEEWORLDEEWORLD

Part Number

Search

1200DGH400JB3DB

Description
Strain Guage Sensor, Gage, 0Psi Min, 4000Psi Max, 0.5%, 1-11V, Cylindrical,
CategoryThe sensor    Sensor/transducer   
File Size507KB,4 Pages
ManufacturerGems Sensors & Controls
Download Datasheet Parametric View All

1200DGH400JB3DB Overview

Strain Guage Sensor, Gage, 0Psi Min, 4000Psi Max, 0.5%, 1-11V, Cylindrical,

1200DGH400JB3DB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Reach Compliance Codecompliant
Maximum accuracy(%)0.5%
shellSTAINLESS STEEL
Nominal offset1V
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output range1-11V
Output typeANALOG VOLTAGE
Package Shape/FormCYLINDRICAL
port type1/4 NPT MALE
Maximum pressure range4000 Psi
Minimum pressure range
Pressure sensing modeGAGE
Sensor/Transducer TypePRESSURE SENSOR,STRAIN GUAGE
Maximum supply voltage35 V
Minimum supply voltage1.5 V
Termination typeDIN 9.4MM W/O MATE
Base Number Matches1
How to generate a trapezoidal waveform using TINA-TI?
How to use TINA-TI to generate a trapezoidal wave? The waveform is as shown in the picture....
qwqwqw2088 Analogue and Mixed Signal
There is a problem with the compilation, please help! Urgent! Urgent!
Error: Node instance "inst" instantiates undefined entity "aab" This is what I encountered after compiling. To explain, the aab module is a component compiled by me using the vhdl language. This sente...
eeleader FPGA/CPLD
C language uses binary tree to parse polynomials and evaluate
It mainly realizes the analysis of polynomial data calculation. If there is a need to make a simple calculator based on a single-chip microcomputer, then it is sufficient.#include stdio.h #include str...
liu583685 stm32/stm8
This UCos
This uCOS has hit me hard. I could barely use it before, but it's getting more and more annoying. Porting a GUI makes me laugh and cry~~~ I have to work harder~~~...
Yehhon Real-time operating system RTOS
Experts please come in, find the greatest common divisor VHDL language program!
VHDL language program to find the greatest common divisor! Urgent, thank you!!...
matin FPGA/CPLD
Ask simple questions
Can an FPGA be made into two unrelated blocks, such as a NIOS core and a combinational logic circuit. Can the two exist at the same time? If so, do they have to share a common clock?...
cafppla FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 775  374  2649  1758  2674  16  8  54  36  30 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号