MXED102
240-Channel OLED Column Driver
Features
•
CMOS High Voltage Process: 9V-30V Display Panel
Supply Compatible
•
240 Output Channels, Cascadable
•
Token-Based Bidirectional Data Transfer: Direct User
Control of Scan Rate
•
Current Source Magnitude User Control: 4 µA to 1 mA
•
6-Bit Monochromatic/Color Gray-Scale User Control
•
Current matching accuracy: ± 2% ± 1.5 µA intra-die
± 1% inter-die
•
Monochromatic/Color Voltage Precharge Options
•
Built-In A-to-D Converter Monitoring of Display Panel
Characteristics
•
3.3 V to 5 V logic supply
•
Up to 35 MHz clock frequency
•
Gold-Bumped Die @ 60 micron Output Pitch
•
TCP packaging
•
Companion to Clare Micronix MXED202
128-Channel OLED Row Driver
Column Driver Block Diagram
Description
The MXED102 is Clare’s second-generation OLED col-
umn driver offering, which supports up to 240-mono-
chromatic or 80-color OLED pixels. The MXED102's
exceptionally tight current-matching of adjacent and
cascaded outputs, precharge options, and OLED moni-
toring capability, ensures uniform luminance and high-
quality greyscaling in both monochromatic and RGB
mode. This is the first ASSP production driver for OLED
module OEM's building a new standard in flat-panel dis-
plays.
For All Passive-Matrix Organic-Light-Emitting-
Diode Displays
•
Monochrome and Color
•
Small-Molecule and Polymer
•
Current-Sourcing Anode Drivers
Preliminary
DS-MXED102-R2
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1
MXED102
PRELIMINARY ELECTRICAL DATA SHEET
Preliminary
This document is a specification for a digital data driver for Passive Matrix Organic Light Emitting Diode (OLED) and
Polymer Light Emitting displays (PLED, PolyLED, LEP, . . . ,etc) with anodes connected to the columns. The output
stage of each channel has a resistive switch to an on chip generated voltage used during precharge and a current
source used during data output to minimize non-uniformity caused by spatial and temporal variations of the LED
characteristics and by line resistances. The data driver chip is manufactured in a high voltage (30 V) CMOS process
and provided in bumped die and TCP (Tape Carrier Package) form.
Description of Operation:
Overview: The MXED102 is configured via a serial port, and pixel data is updated on a per-row basis via a parallel
data bus.
Dynamic Pixel Control: Gray-Scale Control data is loaded into the 6-bit Column Exposure Counters each row scan
time, while the previously loaded data is being output to the OLED Display Panel. The control data sets the expo-
sure time from 0 to 63 Exposure Clock times. Successive counters are accessed upon coincidence with the token
bit, which is shifted the length of the MXED102 by the Token Shift Clock. In 6-bit Data Mode, Databus C {DC(5-0)}
is used to enter per-pixel data, and the Token traverses length of the Chip in 240 Token Shift Clocks. In 18-bit Data
Mode, Databusses A, B, and C are used to load three successive pixels in parallel, and the Token traverses length
of the Chip in 80 Token Shift Clocks.
Chip Configuration: A display controller may use the serial bus to set the characteristics of all column driver ICs by
writing to all column driver ICs in parallel. During write, the controller writes the entire data packet. The controller
can also interrogate a single column driver IC, whose MASTER pin is pulled high. Only one column driver IC on a
given bus can be designated as master. During read, the controller writes the preamble, start of frame delimiter, reg-
ister address, and turn around bits. It then tri-states for the bus tri-state and data bits and reads the data.
Color/Monochrome: The MXED102 supports three-each interleaved column Current Magnitude settings and three
Precharge Voltages, A,B and C, which may be mapped to R,G,B. Monochrome mode is selected by setting the
Color control bit to zero, in which case the Current Magnitude and Precharge Voltage is common.
Package and Pin Out
Below is a diagram of the chip pinout:
MXED102 OLED/PLED Column Driver IC Pad Order
(NOT TO SCALE)
(DIE NOT FLIPPED)
2
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Rev. 2
Preliminary
Pin List
Name
VDDA,
VDDB,
VDDC
VCC
GND
GNDA
ISHRT
PRECHA,
PRECHB,
PRECHC
MASTER_IN
MASTER_OUT
RSTB
CLKSH
I
O
I
I
-
-
-
-
O/A
Logic supply:
Ground:
Analog ground:
-
I/O/A
Description
High voltage supply A/B/C:
MXED102
Ground used to short output channels: There can be high currents on this line. It
should be separated from the circuit ground pads (GND) to prevent ground bounce.
Precharge A/B/C: Column precharge voltage outputs. PRECHA/B/C should be tied
to PRECHA/B/C of all other column drivers to ensure a uniform display precharge
and should be bypassed to ground with a capacitor at least 50 times the display
capacitance.
Master In: High input implies chip is master. This input is pulled low internally.
Master Out: MASTER_IN delayed by 1 LE clock cycle, sampled on rising edge of LE.
Reset Bar: Input signal used to reset digital logic for test purposes. This input is
pulled high internally.
Token Shift Clock: Input signal used to shift tokens down the length of the driver IC
and latch data into the corresponding columns. The direction of token shift is deter
mined by DIRTKN pin.
Left Token Bit: Input for shift right, output for shift left. Signal is used to pass the
tokens into and out of the driver IC. High state represents the presence of token.
Right Token Bit: Input for shift left, output for shift right. Signal is used to pass the
tokens into and out of the driver IC. High state represents the presence of token.
Token Direction Input: Input signal which, when high, causes the token to shift left to
right in the driver IC. A low signal causes the token to shift right to left. In the paral
lel data mode the token passes through the chip in 80 CLKSH clocks, in the serial
data mode the token passes through the chip in 240 CLKSH clocks. This input is
pulled high internally.
Latch Enable: Input signal used to begin data output. When data output begins, new
data input for the following row can begin.
Data A/B/C: Signal buses used to input the exposure data.
LTKNB
RTKNB
DIRTKN
I/O
I/O
I
LE
DA(5-0),
DB(5-0),
DC(5-0)
CLKEX
I
I
I
Exposure Clock: Input signal used to clock the driver IC's exposure counter from 0 to
63 for a row exposure. The signal must be cycled at least 64 times between LE
pulses to completely cycle the counter. Cycles of CLKEX beyond 64 will have no
effect.
Serial Clock: Clock to write serial data into all column drivers or read serial data from
the master column driver.
Serial Data: Serial data written to all column drivers or read from the master column
driver.
Initiate A/D sample. This input is pulled low internally.
CLKSER
SDATA
SAMPLE
I
I/O
I
Rev. 2
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3
MXED102
Pin List (continued)
AD_IN
A
TESTA,
TESTB,
TESTC
I1TRIM
(6:0)
I2TRIM
(3:0)
VTRIM
(3:0)
I2_TST
IOUT(240-1)
CLK_ROW
A
Preliminary
A to D Input: The part can do an A to D conversion on the voltage on this input.
Test Outputs: The A, B, and C driver bank outputs are muxed to the TESTA, TESTB,
and TESTC pads respectively when these pads are pulled low. During normal
operation they are left open or tied to VDD.
Current Source 1 Trim: These pins must be left open.
Current Source 2 Trim: These pins must be left open.
Voltage Source Trim: These pins must be left open.
Current Source 2 Monitor: This pin must be left open.
Channel Outputs: The outputs of the driver IC that directly drives the display panel
Row Clock: Signal intended to drive the row driver IC shift data clock
A
A
A
A
A
O
PCB_ROW
O
Row Precharge: Signal intended to drive the row driver IC precharge input
Note: A => analog, I => digital input, O => digital output
ELECTRICAL SPECIFICATIONS
Positive currents flow into the part, negative currents flow out of the part, largest currents are currents with the great-
est absolute magnitude.
Absolute Maximum Ratings:
Parameter
Ambient temp
Low voltage supply
High voltage supply
Operating Conditions:
Unless otherwise stated, all parameters are specified for the following operating conditions.
Parameter
Ambient temp
Low voltage supply
High voltage supplies
Sym
TA
VCC
VDDA,
VDDB, VDDC
Operating
Condition
-
-
-
Min
0
3.0
9.0
Typ
-
-
-
Max
70
5.5
30
Units
o
Operating Condition
-
-
-
Min
-65
-0.3
-0.3
Typ
-
-
-
Max
155
7.0
35.0
Units
o
C
V
V
C
V
V
Supply Currents:
Parameter
High voltage supply
current during standby
Internal high voltage
supply current during
operation
Low voltage supply
current during standby
Low voltage supply
current during operation
4
Sym
IDD
(stby)
IDD
(int)
Operating
Condition
-
Current from VDD not
flowing out outputs or
into precharge circuit
Iout = per channel
-
-
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Min
-
Typ
-
Max
TBD
14 mA+
12xIout
Units
uA
mA
-
-
ICC
(stby)
ICC
-
-
-
-
TBD
10
uA
mA
Rev. 2
Preliminary
Digital Inputs:
Parameter
Input low voltage
Input high voltage
Input current
Digital Outputs:
Parameter
Output low voltage
Output high voltage
Output rise/fall time
Sym
VOL
VOH
TRF
Operating Condition
Iout = 100 uA
Iout = -100 uA
10 to 90 %, Cload=5 pF
Min
-
VCC-0.4
-
Typ
-
-
-
Max
0.4
-
2.0
Sym
VIL
VIH
II
Operating Condition
-
-
-
Min
-
VCC-0.5
-10
Typ
-
-
-
Max
0.5
-
10
MXED102
Units
V
V
uA
Units
V
V
nS
Serial Configuration Bus:
Bus Operation:
The controller uses the serial bus to set the characteristics of all column driver ICs by writing to all column
driver ICs in parallel. During write, the controller writes the entire data packet. The controller can also inter
rogate a single column driver IC, who's MASTER pin is pulled high. Only 1 column driver IC on a given bus
can be designated as master. During read, the controller writes the preamble, start of frame delimiter, reg
ister address, and turn around bits. It then tri-states for the bus tri-state and data bits and reads the data.
Data Packet:
The data packet consists of:
- 14 bit preamble of all 1's
- 2 bit start of frame delimiter (SFD)
- 6 bit register address - MSB first
- 1 turn around bit (TA)
- 1 bus tristate (BT)
- 8 bit data packet - MSB first
Write => write data to all column driver ICs
Read => read data from master column driver IC
Data order => Preamble first, data last; MSB first, LSB last
R/W
write
read
Preamble
1111 1111 1111 11
1111 1111 1111 11
SFD
00
01
Reg Address
AAAA AA
AAAA AA
TA
0
0
BT
0
Z
Data
DDDD DDDD
DDDD DDDD
Rev. 2
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