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MX98715AEC-E

Description
SINGLE CHIP FAST ETHERNET NIC CONTROLLER - ENHANCED VERSION
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size157KB,39 Pages
ManufacturerMacronix
Websitehttp://www.macronix.com/en-us/Pages/default.aspx
Download Datasheet Parametric Compare View All

MX98715AEC-E Overview

SINGLE CHIP FAST ETHERNET NIC CONTROLLER - ENHANCED VERSION

MX98715AEC-E Parametric

Parameter NameAttribute value
Parts packaging codeQFP
package instructionFQFP,
Contacts128
Reach Compliance Codeunknow
Address bus width32
boundary scanNO
Bus compatibilityPCI
maximum clock frequency25 MHz
Maximum data transfer rate12.5 MBps
External data bus width32
JESD-30 codeR-PQFP-G128
JESD-609 codee0
length20 mm
low power modeYES
Number of serial I/Os1
Number of terminals128
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Package shapeRECTANGULAR
Package formFLATPACK, FINE PITCH
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
width14 mm
uPs/uCs/peripheral integrated circuit typeSERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches1
ADVANCED INFORMATION
MX98715AEC-E
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
- ENHANCED VERSION
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD.
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and category 5 UTP
cable
• Fully comply to PCI spec. 2.1 with clock frequency up
to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.1
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Supports 3 kinds of wake up events defined in Net-
work Device Class Power Management Spec 1.0.
Including:
- Magic Packet
TM
- Link Change(link-on)
- Wake Up Frame
• Supports IEEE802.3x Frame Based Flow Control
scheme in full duplex mode.
• Supports early interrupt on both transmit and receive
operations.
• 100/10 Base-T NWAY auto negotiation function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization, best fit in server and windows appli-
cation.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM address and 128 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package/LQPF package
( Magic packet technology is a trademark of advanced Micro De-
vice Corp. )
2. GENERAL DESCRIPTIONS
The MX98715AEC-E controller is an IEEE802.3u com-
pliant single chip 32-bit full duplex, 10/100Mbps highly
integrated Fast Ethernet combo solution, designed to
address high performance local area networking (LAN)
system application requirements.
MX98715AEC-E's PCI bus master architecture delivers
the optimized performance for future high speed and
powerful processor technologies. In other words, the
MX98715AEC-E not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715AEC-E uses drivers that are backward com-
patible with the original MXIC MX98713 series control-
lers.
The MX98715AEC-E contains a PCI local bus glueless
interface, a Direct Memory Access (DMA) buffer man-
agement unit, an IEEE802.3u-compliant Media Access
Controller (MAC), large Transmit and Receive FIFOs,
and an on-chip 10 Base-T and 100 Base-TX transceiver
simplifying system design and improving high speed sig-
nal quality. Full-duplex operation are supported in both
10 Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-ne-
gotiation, the MX98715AEC-E-based adapter allows a
single RJ-45 connector to link with the other IEEE802.3u-
compliant device without re-configuration.
In MX98715AEC-E, an innovative and proprietary de-
sign "Adaptive Network Throughput Control" (ANTC) is
built-in to configure itself automatically by MXIC's driver
based on the PCI burst throughput of different PCs. With
this proprietary design, MX98715AEC-E can always
optimize its operating bandwidth, network data integrity
and throughput for different PCs.
The MX98715AEC-E features Remote-Power-On and Re-
mote-Wake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
P/N:PM0676
REV. 0.2, MAR. 04, 2000
1

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