MX98715AEC-C datasheet, PDF - EEWORLD Datasheet

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MX98715AEC-C: DescriptionSINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION; CategoryThe embedded processor and controller Microcontrollers and processors; File Size158KB，39 Pages; ManufacturerMacronix; Websitehttp://www.macronix.com/en-us/Pages/default.aspx

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MX98715AEC-C Overview

SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION

MX98715AEC-C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	FQFP, QFP128,.67X.93,20
Contacts	128
Reach Compliance Code	unknow
Address bus width	32
boundary scan	NO
Bus compatibility	PCI
maximum clock frequency	25 MHz
Maximum data transfer rate	12.5 MBps
External data bus width	32
JESD-30 code	R-PQFP-G128
JESD-609 code	e0
length	20 mm
low power mode	YES
Number of serial I/Os	1
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum slew rate	200 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches	1

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ADVANCED INFORMATION

MX98715AEC-C

1. FEATURES

SINGLE CHIP FAST ETHERNET NIC CONTROLLER

- CRYSTAL VERSION

• Supports IEEE802.3x Frame Based Flow Control

scheme in full duplex mode.

• Supports early interrupt on both transmit and receive

operations.

• 100/10 Base-T NWAY auto negotiation function

• Large on-chip FIFOs for both transmit and receive

operations without external local memory

• Bus master architecture with linked host buffers deliv-

ers the most optimized performance

• 32-bit bus master DMA channel provides ultra low

CPU utilization, best fit in server and windows appli-

cation.

• Proprietary Adaptive Network Throughput Control

(ANTC) technology to optimize data integrity and

throughput

• Support up to 64K bytes boot ROM interface

• Three levels of loopback diagnositic capability

• Support a variety of flexible address filtering modes

with 16 CAM address and 128 bits hash

• MicroWire interface to EEPROM for customer's IDs

and configuration data

• Single +5V power supply, CMOS technology, 128-pin

PQFP package/LQPF package

( Magic packet technology is a trademark of advanced Micro De-

vice Corp. )

• A single chip solution integrates 100/10 Base-T fast

Ethernet MAC, PHY and PMD.

• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.

• Support DMI 2.0 management.

• Support Intel PXE remote boot device.

• Fully comply to IEEE 802.3u specification.

• Operates over 100 meters of STP and category 5 UTP

cable.

• Fully comply to PCI spec. 2.1 with clock frequency up

to 33MHz.

• Fully comply to Advanced Configuration and Power

Interface (ACPI) Rev 1.1

• Fully comply to PCI Bus Power Management Inter-

face spec. Rev 1.1

• Support full and half duplex operations in both 100

Base-TX and 10 Base-T mode.

• Supports 3 kinds of wake up events defined in Net-

work Device Class Power Management Spec 1.0.

Including:

- Magic Packet

- Link Change(link-on)

- Wake Up Frame

2. GENERAL DESCRIPTIONS

The MX98715AEC-C controller is an IEEE802.3u com-

pliant single chip 32-bit full duplex, 10/100Mbps highly

integrated Fast Ethernet combo solution, designed to

address high performance local area networking (LAN)

system application requirements.

MX98715AEC-C's PCI bus master architecture delivers

the optimized performance for future high speed and pow-

erful processor technologies. In other words, the

MX98715AEC-C not only keeps CPU utilization low while

maximizing data throughput, but it also optimizes the

PCI bandwidth providing the highest PCI bandwidth uti-

lization. To further reduce maintenance costs the

MX98715AEC-C uses drivers that are backward com-

patible with the original MXIC MX98713 series control-

lers.

The MX98715AEC-C contains a PCI local bus glueless

interface, a Direct Memory Access (DMA) buffer man-

agement unit, an IEEE802.3u-compliant Media Access

Controller (MAC), large Transmit and Receive FIFOs, and

an on-chip 10 Base-T and 100 Base-TX transceiver sim-

plifying system design and improving high speed signal

quality. Full-duplex operation are supported in both 10

Base-T and 100 Base-TX modes that increases the

controller's operating bandwidth up to 200Mbps.

Equipped with intelligent IEEE802.3u-compliant auto-

negotiation, the MX98715AEC-C-based adapter allows

a single RJ-45 connector to link with the other

IEEE802.3u-compliant device without re-configuration.

In MX98715AEC-C, an innovative and proprietary de-

sign "Adaptive Network Throughput Control" (ANTC) is

built-in to configure itself automatically by MXIC's driver

based on the PCI burst throughput of different PCs. With

this proprietary design, MX98715AEC-C can always

optimize its operating bandwidth, network data integrity

and throughput for different PCs.

The MX98715AEC-C features Remote-Power-On and Re-

mote-Wake-Up capability and is compliant with the Ad-

vanced Configuration and Power Interface version 1.0

P/N:PM0655

REV. 0.3, MAY. 04, 2000

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