ADVANCED INFORMATION
MX98715AEC-D
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and cat 5 UTP cable
• Fully comply to PCI spec. 2.1 up to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.1
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Supports 3 kinds of wake up events defined in Net-
work Device Class Power Management Spec 1.0.
Including:
- Magic Packet
- Link Change (link-on)
- Wake Up Frames
• Supports IEEE802.3x Frame Based Flow Control
scheme in full duplex mode.
• Supports early interrupt on both transmit and receive
operations. • 100/10 Base-T NWAY auto-negotiation
function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization suitable for server and windows appli-
cations.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM addresses and 128 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package.
( Magic packet technology is a trademark of advanced Micro De-
vice Corp. )
2. GENERAL DESCRIPTIONS
The MX98715AEC-D controller is an IEEE802.3u com-
pliant single chip 32-bit full duplex, 10/100Mbps highly
integrated Fast Ethernet combo solution, designed to
address high performance local area networking (LAN)
system application requirements.
MX98715AEC-D's PCI bus master architecture delivers
the optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715AEC-D not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715AEC-D uses drivers that are backward com-
patible with the original MXIC MX98715 series control-
lers.
The MX98715AEC-D contains a PCI local bus glueless
interface, a Direct Memory Access (DMA) buffer man-
agement unit, an IEEE802.3u-compliant Media Access
Controller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715AEC-D-based adapter allows
a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
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MX98715AEC-D
In MX98715AEC-D, an innovative and proprietary de-
sign "Adaptive Network Throughput Control" (ANTC) is
built-in to configure itself automatically by MXIC's driver
based on the PCI burst throughput of different PCs. With
this proprietary design, MX98715AEC-D can always
optimize its operating bandwidth, network data integrity
and throughput for different PCs.
The MX98715AEC-D features Remote-Power-On and Re-
mote-Wake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
(ACPI). This support enables a wide range of wake-up
capabilities, including the ability to customize the con-
tent of specified packet which PC should respond to,
even when it is in a low-power state. PCs and worksta-
tions could take advantage of these capabilities of be-
ing waked up and served simultaneiously over the net-
work by remote server or workstation. It helps organiza-
tions reduce their maintenance cost of PC network.
The 32-bit multiplexed bus interface unit of
MX98715AEC-D provides a direct interface to a PCI lo-
cal bus, simplifing the design of an Ethernet adapter in a
PC system. With its on-chip support for both little and
big endian byte alignment, MX98715AEC-D can also ad-
dress non-PC applications.
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LANWAKE
VDD
VDD
GND
GND
GND
INTAB
RTX
VDD
RSTB
PCICLK
GNTB
REQB
AD24
AD25
GND
GND
VDD
AD27
AD28
AD30
GND
AD31
AD26
AD29
CBEB3
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128
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
GND
GND
CKREF
VDD
RDA
GND
VDD
LED3
LED2
LED1
BPA15(LED0)
BPA14
BPA13
GND
VDD
BPA12
BPA11
BPA10
BPA9
BOEB
BPA8
BPA7
BPA6
BPA5
GND
VDD
RXIN
RXIP
VDD
GND
GND
VDD
TXON
TXOP
GND
EQTEST2
RTX2EQ
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PAR
IDSEL
GND
AD23
AD22
GND
3. PIN CONFIGURATIONS
AD21
AD20
VDD
AD19
AD18
GND
AD17
AD16
CBEB2
FRAMEB
GND
IRDYB
TRDYB
DEVSELSB
MX98715AEC-D
3
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VDD
VDD
GND
GND
GND
BPA2
BPA3
BPD7
BPD6
BPD5
BPD4
BPD3
BPD2
BPD1
EECS
BPA1(EEDI)
BPA0(EECK)
BPD0(EED0)
STOPB
VDD
PERRB
SERRB
CBEB1
AD15
GND
AD14
AD13
VDD
AD12
AD11
AD10
GND
CBEB0
BPA4
MX98715AEC-D
REV. 0.1, FEB. 05, 2001
MX98715AEC-D
4. PIN DESCRIPTION ( 128 PIN PQFP )
( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )
Pin Name
AD[31:0]
Type
T/S
Pin No
116, 117
119,120,
122,124,
125,127,
3,4,6,7,9,
10,12,13,
26,28,29,
31-33,35,
36,38,39,
41,42,44,
45,47,48
128,14
25,37
128 Pin Function and Driver
PCI address/data bus: shared PCI address/data bus lines. Little or big endian
byte ordering are supported.
CBE[3:0]
T/S
FRAMEB
S/T/S 15
TRDYB
IRDYB
S/T/S 18
S/T/S 17
DEVSELB S/T/S 19
IDSEL
I
1
113
112
110
111
23
PCICLK
I
RSTB
I
LANWAKE O
INTAB
SERRB
PERRB
O/D
O/D
S/T/S 22
PCI command and byte enable bus: shared PCI command byte enable bus,
during the address phase of the transaction, these four bits provide the bus
command. During the data phase, these four bits provide the byte enable.
PCI FRAMEB signal: shared PCI cycle start signal, asserted to indicate the
beginning of a bus transaction. As long as FRAMEB is asserted, data
transfers continue.
PCI Target ready: issued by the target agent, a data phase is completed on
the rising edge of PCICLK when both IRDYB and TRDYB are asserted.
PCI Master ready: indicates the bus master's ability to complete the current
data phase of the transaction. A data phase is completed on any rising edge
of PCICLK when both IRDYB and TRDYB are asserted.
PCI slave device select: asserted by the target of the current bus access.
When 98715ALEC is the initiator of current bus access, the target must as
sert DEVSELB within 5 bus cycles, otherwise cycle is aborted.
PCI initialization device select: target specific device select signal for
configuration cycles issued by host.
PCI bus clock input: PCI bus clock range from 16MHz to 33MHz.
PCI bus reset: host system hardware reset.
LAN wake up signal:asserts high to indicate a magic packet has been de-
tected in Packet enable mode.
PCI bus interrupt request signal: wired to INTAB line.
PCI bus system error signal: If an address parity error is detected and CFCS
bit 8 is enabled, SERRB and CFCS's bit 30 will be asserted.
PCI bus data error signal: As a bus master, when a data parity error is
detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will be
asserted. As a bus target, a data parity error will cause PERRB to be
asserted.
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MX98715AEC-D
Pin Name
PAR
STOPB
REQB
GNTB
BPA1
(EEDI)
BPA0
(EECK)
BPA[14:0]
O
77-76,
73-70,
68-60
78
Type
T/S
Pin No
24
128 Pin Function and Driver
PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE
bus.
PCI Target requested transfer stop signal: as bus master, assertion of STOPB
cause MX98715AEC-D either to retry, disconnect, or abort.
PCI bus request signal: to initiate a bus master cycle request
PCI bus grant acknowledge signal: host asserts to inform MX98715AEC-D
that access to the bus is granted
Boot PROM address bit 1(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM data in(EECS=1): EEPROM serial data input pin.
Boot PROM address bit 0(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
Boot PROM address line.
Boot PROM address line 15.
Programmable LED pin 0:
CSR9.28=1
Set the LED as Link Speed (10/100)LED.
CSR9.28=0
Set the LED as Activity LED.
Default is activity LED after reset.
<Note>:This pin acts as LED0 normally. It automatically switch to Boot
PROM address 15 function while accessing Boot PROM.
Boot PROM data line 0(EECS=0): boot PROM or flash data line 0.
EEPROM data out(EECS=1): EEPROM serial data outpin(during reset
initialization).
Boot PROM data lines: boot PROM or flash data lines 7-0.
EEPROM Chip Select pin.
Boot PROM Output Enable.
Connecting an external resistor to ground, Resistor value=510 ohms
Connecting an external resistor to ground, Resistor value=510 ohms
Connecting an external resistor to ground, Resistor value=1.5K ohms.
Not connected.
Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
S/T/S 20
T/S
I
O
115
114
61
O
60
BPA15
/LED0
O
BPD0
(EEDO)
BPD[7:0]
EECS
BOEB
RDA
RTX
RTX2EQ
EQTEST2
RXIP
RXIN
T/S
58
T/S
O
O
O
O
O
I
I
I
51-58
59
69
84
103
102
101
93
92
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