STuW81300
Wideband RF/microwave PLL fractional/integer frequency
synthesizer with integrated VCOs and LDOs
Datasheet
-
production data
•
Supply voltage: 3.0 V to 5.4 V
•
Small size exposed pad VFQFPN36 package
6x6x1.0 mm
•
Process: BICMOS 0.25 µm SiGe
Applications
VFQFPN36
•
Infrastructure equipment
•
Satellite communications for terrestrial
applications
•
Other wireless communication systems
Table 1. Device summary
Order Code
STUW81300-1T
STUW81300-1TR
STUW81300T
STUW81300TR
Package
VFQFPN36
VFQFPN36
VFQFPN36
VFQFPN36
Packing
Tray
Tape and reel
Tray
Tape and reel
Features
•
Output frequency range: 1.925 GHz to 16 GHz
– RF out 1 (VCO, VCO÷2): 1.925-8.0 GHz
– RF out 2 (VCO x 2): 7.7-16.0 GHz
•
Very low noise
– Normalized phase noise floor: -227 dBc/Hz
– VCO phase noise (6.0 GHz): -131 dBc/Hz
@ 1 MHz offset
– Noise floor (6.0 GHz): -158 dBc/Hz
– Phase noise (12 GHz): -125 dBc/Hz
@ 1 MHz offset
– Noise floor (12 GHz): -154 dBc/Hz
•
Integrated VCOs with fast automatic center
frequency calibration
•
External VCO option with 5 V charge pump
•
Fundamental VCO rejection at doubler output
higher than 20 dB
•
Internally broadband matched RF outputs
delivering +6 dBm @6 GHz and +4 dBm
@12 GHz single-ended
•
Integrated low noise LDOs
•
Maximum phase detector frequency: 100 MHz
•
Exact frequency mode
•
Differential reference clock input (LVDS and
LVECPL compliant) supporting up to 800 MHz
•
Integrated reference crystal oscillator core
•
R/W SPI interface
•
Logic compatibility/tolerance 1.8 V/3.3 V
Description
The STuW81300 includes a dual architecture
frequency synthesizer (Fractional-N and Integer-
N), four low phase noise VCOs with a fast
automatic center frequency calibration providing a
very wide frequency range, from 1.925 GHz to
16 GHz, with a single device.
The STuW81300 optimizes size and cost of the
final application by the integration of low noise
LDO voltage regulators and internally matched
broadband RF outputs.
Additional features include a crystal oscillator
core, external VCO mode, output mute function
and low power mode to trade current
consumption with phase noise performance
and/or output level.
August 2019
This is information on a product in full production.
DS11314 Rev 6
1/63
www.st.com
Contents
STuW81300
Contents
1
2
3
4
5
6
7
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1
7.2
7.3
7.4
Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PLL N divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fractional spurs and compensation mechanism . . . . . . . . . . . . . . . . . . . 25
7.4.1
7.4.2
7.4.3
PFD delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Charge pump leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Down-split current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Fast lock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Cycle slip reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Voltage controlled oscillators (VCOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RF output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Low-power functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LDO voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STuW81300 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STuW81300 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STuW81300 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/63
DS11314 Rev 6
STuW81300
Contents
7.17
7.18
Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Example register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1
8.2
8.3
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Thermal PCB design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Robust VCO calibration over full temperature range . . . . . . . . . . . . . . . . 53
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1
VFQFPN36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10
11
Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DS11314 Rev 6
3/63
3
List of tables
STuW81300
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Phase noise specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current value versus selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SPI Register map (address 12 to 15 not available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Example of data for robust VCO calibration routine to be stored in the
application memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VFQFPN - 36 pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
STuW81300 evaluation-kit order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4/63
DS11314 Rev 6
STuW81300
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
STuW81300 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCO open loop phase noise (5 V supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Closed loop phase noise (5 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VCO Open loop phase noise at 5.3 GHz vs. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VCO open loop phase noise over Frequency vs. supply . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Single sideband integrated phase noise vs. frequency and supply (F
PFD
=50 MHz) . . . . . 20
Average K
VCO
over VCO frequency and supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase noise and fractional spurs at 5952.5 MHz vs. supply (F
PFD
=50 MHz) . . . . . . . . . . 20
Phase noise and fractional spurs at 11502.5 MHz vs. supply (F
PFD
=50 MHz) . . . . . . . . . 20
Output power level vs. temperature – RF1 output (5.0 V supply) . . . . . . . . . . . . . . . . . . . . 20
Output power level vs. temperature– RF2 output (5.0 V supply) . . . . . . . . . . . . . . . . . . . . 20
VCO feedthrough at RF2 output vs. fundamental VCO frequency . . . . . . . . . . . . . . . . . . . 21
Typical spur level vs offset from 12 GHz (5.0 V supply, F
PFD
=50 MHz). . . . . . . . . . . . . . . 21
Typical spur level at PFD offset over carrier frequency (5.0 V supply) . . . . . . . . . . . . . . . . 21
10 kHz and 2.5 MHz fractional spur (integer boundary, 5.0 V supply, F
PFD
=50 MHz) . . . . 21
Frequency settling with VCO calibration – wideband view . . . . . . . . . . . . . . . . . . . . . . . . . 21
Frequency settling with VCO calibration – narrowband view . . . . . . . . . . . . . . . . . . . . . . . 21
Overall current consumption vs. temperature (5.0 V supply, F
PFD
=50 MHz) . . . . . . . . . . . 22
Overall current consumption vs. temperature (3.6 V supply, F
PF
D=50 MHz). . . . . . . . . . . 22
Figure of merit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reference clock buffer configurations: single-ended (A), differential (B), crystal mode (C) 23
PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
VFQFPN - 36 pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
VFQFPN - 36 pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DS11314 Rev 6
5/63
5
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