STM32MP157C datasheet, PDF - EEWORLD Datasheet

STM32MP157C: DescriptionMPU with Arm Dual Cortex-A7 650 Mhz, Arm Cortex-M4 real-time coprocessor, 3D GPU, TFT/MIPI DSI display, FD-CAN, secure boot and encryption; File Size3MB，259 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM32MP157C Overview

MPU with Arm Dual Cortex-A7 650 Mhz, Arm Cortex-M4 real-time coprocessor, 3D GPU, TFT/MIPI DSI display, FD-CAN, secure boot and encryption

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STM32MP157C/F

Arm

dual Cortex

-A7 800 MHz + Cortex

-M4 MPU, 3D GPU,

TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, crypto

Datasheet

production data

Features

LFBGA

TFBGA

Core

•

32-bit dual-core Arm

Cortex

-A7

– L1 32-Kbyte I / 32-Kbyte D for each core

– 256-Kbyte unified level 2 cache

– Arm

NEON™ and Arm

TrustZone

•

32-bit Arm Cortex -M4 with FPU/MPU

– Up to 209 MHz (Up to 703 CoreMark

)

LFBGA448 (18 × 18mm)

LFBGA354 (16 × 16mm)

Pitch 0.8mm

TFBGA361 (12 × 12 mm)

TFBGA257 (10 × 10 mm)

min Pitch 0.5mm

•

DDR memory retention in Standby mode

•

Controls for PMIC companion chip

Low-power consumption

•

Total current consumption down to 2 µA

(Standby mode, no RTC, no LSE, no

BKPSRAM, no RETRAM)

Memories

•

External DDR memory up to 1 Gbyte

– up to LPDDR2/LPDDR3-1066 16/32-bit

– up to DDR3/DDR3L-1066 16/32-bit

•

708 Kbytes of internal SRAM: 256 Kbytes of

AXI SYSRAM + 384 Kbytes of AHB SRAM +

64 Kbytes of AHB SRAM in Backup domain

and 4 Kbytes of SRAM in Backup domain

•

Dual mode Quad-SPI memory interface

•

Flexible external memory controller with up to

16-bit data bus: parallel interface to connect

external ICs and SLC NAND memories with up

to 8-bit ECC

Clock management

•

Internal oscillators: 64 MHz HSI oscillator,

4 MHz CSI oscillator, 32 kHz LSI oscillator

•

External oscillators: 8-48 MHz HSE oscillator,

32.768 kHz LSE oscillator

•

6 × PLLs with fractional mode

General-purpose input/outputs

•

Up to 176 I/O ports with interrupt capability

– Up to 8 secure I/Os

– Up to 6 Wakeup, 3 tampers, 1 active

tamper

Security/safety

•

Secure boot, TrustZone

peripherals, active

tamper

•

Cortex

-M4 resources isolation

Interconnect matrix

•

2 bus matrices

– 64-bit Arm

AMBA

AXI interconnect, up to

266 MHz

– 32-bit Arm

AMBA

AHB interconnect, up

to 209 MHz

Reset and power management

•

1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)

•

POR, PDR, PVD and BOR

•

On-chip LDOs (RETRAM, BKPSRAM, DSI

1.2 V, USB 1.8 V, 1.1 V)

•

Backup regulator (~0.9 V)

•

Internal temperature sensors

•

Low-power modes: Sleep, Stop and Standby

3 DMA controllers to unload the CPU

•

48 physical channels in total

•

1 × high-speed general-purpose master direct

memory access controller (MDMA)

September 2020

This is information on a product in full production.

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STM32MP157C/F

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1

Dual-core Arm

Cortex

-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1

3.1.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2

3.3

3.4

Arm

Cortex

-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Graphic processing unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.1

3.4.2

External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5

3.6

3.7

3.8

DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 25

TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 26

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.8.1

3.8.2

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.9

3.10

Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.10.1

3.10.2

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.11

3.12

3.13

3.14

3.15

3.16

3.17

3.18

Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 33

3.12.1

IPCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 34

Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 37

Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 37

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Contents

STM32MP157C/F

3.19

3.20

3.21

3.22

3.23

3.24

3.25

3.26

3.27

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

Cyclic redundancy check calculation unit (CRC1, CRC2) . . . . . . . . . . . . 38

Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 38

Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

BAT

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Digital-to-analog converters (DAC1, DAC2) . . . . . . . . . . . . . . . . . . . . . . . 40

Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Digital filter for sigma delta modulators (DFSDM1) . . . . . . . . . . . . . . . . . 41

Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Display serial interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

True random number generator (RNG1, RNG2) . . . . . . . . . . . . . . . . . . . 44

Cryptographic and hash processors (CRYP1, CRYP2 and

HASH1, HASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 45

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.35.1

3.35.2

3.35.3

3.35.4

3.35.5

3.35.6

3.35.7

3.35.8

Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 47

General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,

TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . . 48

Independent watchdog (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . . 48

System window watchdog (WWDG1) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SysTick timer (Cortex-M4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.36

3.37

3.38

3.39

3.40

System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5, I2C6) . . . 52

Universal synchronous asynchronous receiver transmitter

(USART1, USART2, USART3, USART6 and UART4, UART5,

UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5,

SPI6)– inter- integrated sound interfaces (I2S1, I2S2, I2S3) . . . . . . . . . . 53

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STM32MP157C/F

Contents

3.42

3.43

3.44

3.45

3.46

3.47

3.48

3.49

3.50

3.51

Serial audio interfaces (SAI1, SAI2, SAI3, SAI4) . . . . . . . . . . . . . . . . . . . 54

SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 55

Secure digital input/output MultiMediaCard interface

(SDMMC1, SDMMC2, SDMMC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 55

Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 56

USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Gigabit Ethernet MAC interface (ETH1) . . . . . . . . . . . . . . . . . . . . . . . . . . 57

High-definition multimedia interface (HDMI) – Consumer

electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 59

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 128

Embedded reset and power control block characteristics . . . . . . . . . . 130

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 133

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 146

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 148

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STM32MP157C Related Products

	STM32MP157C	STM32MP157F
Description	MPU with Arm Dual Cortex-A7 650 Mhz, Arm Cortex-M4 real-time coprocessor, 3D GPU, TFT/MIPI DSI display, FD-CAN, secure boot and encryption	MPU with Arm Dual Cortex-A7 800 MHz, Arm Cortex-M4 real-time coprocessor, 3D GPU, TFT/MIPI DSI displays, FD-CAN, Secure boot and Cryptography

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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