MX26LV040
Macronix NBit
TM
Memory Family
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE
3V ONLY HIGH SPEED eLiteFlash
TM
MEMORY
FEATURES
• Extended single - supply voltage range 3.0V to 3.6V
• 524,288 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55/70ns
• Low power consumption
- 30mA maximum active current
- 30uA typical standby current
• Command register architecture
- Byte Programming (55us typical)
- Sector Erase (Sector structure 64K-Byte x8)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Status Reply
- Data# polling & Toggle bit for detection of program
and erase operation completion.
• 2,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX26LV040 is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX26LV040 is pack-
aged in 32-pin PLCC, 32-pin TSOP and 32-pin PDIP. It
is designed to be reprogrammed and erased in system
or in standard EPROM programmers.
The standard MX26LV040 offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX26LV040 has separate chip enable (CE#) and output
enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX26LV040 uses a command register to manage this
functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 2,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX26LV040 uses a 3.0V~3.6V VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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MX26LV040
AUTOMATIC PROGRAMMING
The MX26LV040 is byte programmable using the Auto-
matic Programming algorithm. The Automatic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed.
the device automatically times the erase pulse width,
provides the erase verification, and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the sta-
tus of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX26LV040 electri-
cally erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA# Polling and a status bit
toggling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, table 7, for more
information on these status bits.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
The Automatic Erase algorithm automatically programs
the entire array prior to electrical erase. The timing and
verification of electrical erase are controlled internally
within the device.
AUTOMATIC SECTOR ERASE
The MX26LV040 is sector(s) erasable using MXIC's Auto
Sector Erase algorithm. The Automatic Sector Erase
algorithm automatically programs the specified sector(s)
prior to electrical erase. The timing and verification of
electrical erase are controlled internally within the de-
vice. An erase operation can erase one sector, multiple
sectors, or the entire device.
AUTOMATIC SELECT
The auto select mode provides manufacturer and de-
vice identification, through identifier codes output on
Q7~Q0. This mode is mainly adapted for programming
equipment on the device to be programmed with its pro-
gramming algorithm. When programming by high voltage
method, automatic select mode requires VID (11V to 12V)
on address pin A9 and other address pin A6, A1 and A0
as referring to Table 3. In addition, to access the auto-
matic select codes in-system, the host can issue the
automatic select command through the command regis-
ter without requiring VID, as shown in table 4.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
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MX26LV040
TABLE 3. MX26LV040 AUTO SELECT MODE OPERATION
A18 A12
Description
Read
Manufacturer Code
CE# OE# WE#
L
L
L
L
H
H
|
X
X
|
X
X
VID
VID
A13 A10
Silicon ID Device ID
A9
A8
|
A7
X
X
L
L
A6
A5
|
A2
X
X
L
L
L
H
C2H
4FH
A1
A0
Q7~Q0
NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing
incorrect address and data values or writing them in the improper sequence will reset the device to the read mode.
Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H)
commands are valid only while the Sector Erase operation is in progress.
TABLE 4. MX26LV040 COMMAND DEFINITIONS
First Bus
Command
Bus Cycle
Cycle Addr
Reset
Read
Read Silicon ID
Program
Chip Erase
Sector Erase
1
1
4
4
6
6
Second Bus
Cycle
Data Addr
Third Bus
Cycle
Data Addr
Fourth Bus
Cycle
Data Addr
Data
Fifth Bus
Cycle
Addr
Sixth Bus
Cycle
Data Addr
Data
XXXH F0H
RA
RD
55H
55H
55H
55H
555H
555H
555H
555H
90H ADI
A0H PA
DDI
PD
2AAH 55H
2AAH 55H
555H 10H
SA
30H
555H AAH 2AAH
555H AAH 2AAH
555H AAH 2AAH
555H AAH 2AAH
80H 555H AAH
80H 555H AAH
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 4FH for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
3. Address A18-A11 are don't cares for unlock and command cycles.
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