MX26C1000A
1M-BIT [128K x 8] CMOS
MULTIPLE-TIME-PROGRAMMABLE-EPROM
FEATURES
•
•
•
•
•
•
•
128K x 8 organization
+5V operating power supply
+12.75V program/erase voltage
Electric erase instead of UV light erase
Fast access time: 70/90/100/120/150 ns
Totally static operation
Completely TTL compatible
•
•
•
•
Operating current: 30mA
Standby current: 100uA
100 minimum erase/program cycles
Package type:
- 32 pin PDIP
Y
- 32 pin SOP
LOG
- 32 pin PLCC
O
CHN
- 32 pin TSOP(I)
E
GENERAL DESCRIPTION
The MX26C1000A is a 12.75V/5V, 1M-bit MTP
EPROM
TM
(Multiple Time Programmable Read Only
Memory). It is organized as 128K words by 8 bits per
word, operates from a + 5 volt supply, has a static
standby mode, and features fast address location
programming. It is designed to be reprogrammed and
erased by an EPROM programmer or on-board. All
programming/erasing signals are TTL levels, requiring a
D
NTE
E
PAT
T
single pulse. The MX26C1000A supports an intelligent
quick pulse programming algorithm which can result in a
programming time of less than 30 seconds.
This MTP EPROM
TM
is packaged in industry standard 32
pin dual-in-line packages, 32 pinPLCC packages or 32
pin TSOP packages and 32 pin SOP packages.
PIN CONFIGURATIONS
PGM
BLOCK DIAGRAM
CE
CONTROL
LOGIC
OUTPUT
BUFFERS
PDIP/SOP
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
PLCC
VCC
VPP
A12
A15
A16
NC
Q0~Q7
OE
A7
A6
A5
A4
A3
A2
A1
A0
Q0
5
4
1
32
30
29
A14
A13
A8
A9
A0~A16
ADDRESS
INPUTS
.
.
.
.
.
.
.
.
Y-DECODER
.
.
.
.
.
.
.
.
Y-SELECT
MX26C1000A
9
MX26C1000A
25
A11
OE
A10
CE
X-DECODER
1M BIT
CELL
MAXTRIX
13
14
Q1
Q2
GND
17
Q3
Q4
Q5
21
20
Q6
Q7
VCC
GND
VPP
TSOP
A3
A2
A1
A0
Q0
Q1
Q2
GND
Q3
Q4
Q5
Q6
Q7
CE
A10
OE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A4
A5
A6
A7
A12
A15
A16
VPP
VCC
PGM
NC
A14
A13
A8
A9
A11
PIN DESCRIPTION
SYMBOL
A0~A16
Q0~Q7
CE
OE
VPP
NC
VCC
GND
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Output Enable Input
Program Supply Voltage
No Internal Connection
Power Supply Pin (+5V)
Ground Pin
MX261000A
P/N: PM0454
Patent#: US#5,526,307
1
REV.1.5, FEB 10, 1998
MX26C1000A
FUNCTIONAL DESCRIPTION
When the MX26C1000A is delivered, or it is erased, the
chip has all 1000K bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C1000 through the
procedure of programming.
ERASE MODE
The MX26C1000A is erased by an EPROM programmer
or in-system. The device is set up in erase mode when
the A9 = VPP = 12.75V are applied, with VCC = 5V and
PGM = VIL.(Algorithm shown in Figure 3). Erase time
is around 1sec. If the erase is not verified, an additional
erase processes will be repeated for a maximum of 200
times.
PROGRAMMING MODE
PROGRAMMING ALGORITHM
The MX26C1000A is programmed by an EPROM
programmer or on-board. The device is set up in the
programming mode when the programming voltage VPP
= 12.75V is applied, with VCC = 5 V and PGM = VIH
(Algorithm shown in Figure 1). Programming is achieved
by applying a single TTL low level 25us pulse to the PGM
input after addresses and data lines are stable. If the
data is not verified, additional pulses are applied for
a maximum of 20 pulses. After the data is verified, one
25us pulse is applied to overprogram the byte so that
program margin is assured. This process is repeated
while sequencing through each address of the device.
When programming is completed, the data at all the
address is verified at VCC = VPP = 5V
±
10%.
The VCC supply of the MXIC On-Board Programming
Algorithm is designed to be 5V
±
10% particularly to
faciliate the programming operation under the on-board
application environment. But it can also be implemented
in an industrial-standard EPROM programmer.
PROGRAM INHIBIT MODE
Programming of multiple MX26C1000s in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX26C1000 may be common. A
TTL low-level program pulse applied to an MX26C1000A
CE input with VPP = 12.75
±
0.25 V and PGM LOW will
program that MX26C1000A. A high-level CE input
inhibits the other MX26C1000A from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits
to determine that they were correctly programmed.
Verification should be performed with OE and CE, at VIL,
PGM at VIH, and VPP at its programming voltage.
ERASE VERIFY MODE
COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING
ALGORITHM
Besides the On-Board Programming Algorithm, the Fast
Programming Algorithm of MX27C1000 also applies to
MX26C1000A. MXIC Fast Algorithm is the conventional
EPROM programming algorithm and is available in
industrial-standard EPROM programmers. A user of
industrial-standard EPROM programmer can choose
either of the algorithms base on his preference.
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applted, with
VCC = 6.25V and PGM = VIL(or OE = VIH)(Algorithm
is shown in Figure 2). The programming is achieved
by applying a single TTL low level 25~100us pulse is
applied for a maximum of 25 pulses. This process is
repeated while sequencing through each address of the
device. When the programming mode is completed, the
data in all address is verified at VCC = VPP = 5V
±
10%.
Verification should be performed on the erased chip to
determine that the whole chip(all bits) was correctly
erased. Verification should be performed with OE and
CE at VIL, PGM at VIH, and VCC = 5V, VPP = 12.5V
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an MTP that will identify its manufacturer and
device type. This mode is intended for use by the
programming equipment for the purpose of automatically
matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional in the 25°
±
5°C ambient temperature range
C
that is required when programming the MX26C1000A.
To activate this mode, the programming equipment must
force 12.75V on address line A9 of the device. Two
P/N: PM0454
Patent#: US#5,526,307
2
REV.1.5, FEB 10, 1998
MX26C1000A
identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH. All
other address lines must be held at VIL during auto
identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C1000A, these two identifier bytes are given
in the Mode Select Table. All identifiers for the
manufacturer and device codes will possess odd parity,
with the MSB (DQ7) defined as the parity bit.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitance loading of the device. At a minimum, a 0.1
uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be used
between VCC and GND for each of the eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
READ MODE
The MX26C1000A has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C1000A has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is placed
in CMOS standby when CE is at VCC
±
0.3 V. The
MX26C1000A also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state,
independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
P/N: PM0454
Patent#: US#5,526,307
3
REV.1.5, FEB 10, 1998
MX26C1000A
MODE SELECT TABLE
PINS
MODE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Erase
Erase Verify
Program Inhibit
Manufacturer Code
Device Code(26C1000)
CE
VIL
VIL
VIH
VCC
VIL
VIL
VIL
VIL
VIH
VIL
VIL
OE
VIL
VIH
X
X
VIH
VIL
VIH
VIL
X
VIL
VIL
PGM
X
X
X
X
VIL
VIH
VIL
VIH
X
X
X
A0
X
X
X
X
X
X
X
X
X
VIL
VIH
A9
X
X
X
X
X
X
VPP
X
X
VH
VH
VPP
VCC
VCC
VCC
VCC
VPP
VPP
VPP
VPP
VPP
VCC
VCC
OUTPUTS
DOUT
High Z
High Z
High Z
DIN
DOUT
HIGH Z
DOUT
High Z
C2H
D2H
NOTES:
1. VH = 12.0 V
±
0.5 V
2. X = Either VIH or VIL(For auto select)
3. A1 - A8 = A10 - A16 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during
programming.
FIGURE 1. PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 5V
VPP = 12.75V
X=0
PROGRAM ONE 25us PULSE
INTERACTIVE
SECTION
INCREMENT X
YES
X = 20 ?
NO
FAIL
VERIFY BYTE
?
PROGRAM ONE 25us PULSE
PASS
NO
INCREMENT ADDRESS
LAST ADDRESS
FAIL
PROGRAM ONE 25us PULSE
YES
VERIFY SECTION
VCC = VPP = 5V
VERIFY ALL BYTES
?
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0454
Patent#: US#5,526,307
4
REV.1.5, FEB 10, 1998
MX26C1000A
FIGURE 2. COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X=0
PROGRAM ONE 25~100us PULSE
INTERACTIVE
SECTION
INCREMENT X
YES
X = 25?
NO
FAIL
VERIFY BYTE
?
PASS
NO
INCREMENT ADDRESS
LAST ADDRESS
FAIL
YES
VCC = VPP = 5.25V
VERIFY SECTION
VERIFY ALL BYTES
?
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0454
Patent#: US#5,526,307
5
REV.1.5, FEB 10, 1998
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