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ICS9DB108YFLFT

Description
PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, ROHS COMPLIANT, MO-118, SSOP-48
Categorylogic    logic   
File Size106KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

ICS9DB108YFLFT Overview

PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, ROHS COMPLIANT, MO-118, SSOP-48

ICS9DB108YFLFT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP,
Contacts48
Reach Compliance Codecompliant
Is SamacsysN
series9DB
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G48
JESD-609 codee3
length15.875 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals48
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height2.8 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.5 mm
minfmax220 MHz
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS9DB108
Eight Output Differential Buffer for PCI-Express
Recommended Application:
DB800 Intel Yellow Cover part with PCI-Express support.
Output Features:
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Key Specifications:
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
+/- 300ppm frequency accuracy on output clocks
Features/Benefits:
Supports tight ppm accuracy clocks for Serial-ATA
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
Supports undriven differential output pair in PD# and
SRC_STOP# for power management.
Pin Configuration
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
GND
VDD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP#
PD#
GND
48-pin SSOP & TSSOP
0723D—01/08/04
ICS9DB108
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