1CY 7C34 2B
fax id: 6107
CY7C342B
128-Macrocell MAX® EPLDs
Features
•
•
•
•
128 macrocells in 8 LABs
8 dedicated inputs, 52 bidirectional I/O pins
Programmable interconnect array
Advanced 0.65-micron CMOS technology to increase
performance
• Available in 68-pin HLCC, PLCC, and PGA
The 128 macrocells in the CY7C342B are divided into 8 Logic
Array Blocks (LABs), 16 per LAB. There are 256 expander
product terms, 32 per LAB, to be used and shared by the mac-
rocells within each LAB.
Each LAB is interconnected with a programmable interconnect
array, allowing all signals to be routed throughout the chip.
The speed and density of the CY7C342B allows it to be used in a
wide range of applications, from replacement of large amounts of
7400-series TTL logic, to complex controllers and multifunction
chips. With greater than 25 times the functionality of 20-pin PLDs,
the CY7C342B allows the replacement of over 50 TTL devices. By
replacing large amounts of logic, the CY7C342B reduces board
space, part count, and increases system reliability.
Functional Description
The CY7C342B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX architecture is
100% user configurable, allowing the devices to accommodate
a variety of independent logic functions.
Logic Block Diagram
1 (B6)
2 (A6)
32 (L4)
34 (L5)
INPUT/CLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
(A7)
(A8)
(L6)
(K6)
68
66
36
35
SYSTEM CLOCK
LAB A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 9-16
LAB B
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22-32
P
I
A
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 121-128
LAB G
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 102-112
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
4 (A5)
5 (B4)
6 (A4)
7 (B3)
8 (A3)
9 (A2)
10 (B2)
11 (B1)
12 (C2)
13 (C1)
14 (D2)
15 (D1)
17 (E1)
(D11) 57
(D10) 56
(E11) 55
(F11) 53
(F10) 52
18 (F2)
19 (F1)
21 (G1)
22 (H2)
23 (H1)
LAB C
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38-48
LAB F
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86-96
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
24 (J2)
25 (J1)
26 (K1)
27 (K2)
28 (L2)
29 (K3)
30 (L3)
31 (K4)
LAB D
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
MACROCELL 57- 64
3, 20, 37, 54 (B5, G2, K7, E10)
16, 33, 50, 67 (E2, K5, G10, B7)
V
CC
GND
LAB E
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
MACROCELL 73- 80
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
() – PERTAIN TO 68-PIN PGA PACKAGE
C342B-1
MAX is a registered trademark of Altera Corporation.
Warp2
and
Warp3
are registered trademarks of Cypress Semiconductor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
October 1989 – Revised October 1995
CY7C342B
Selection Guide
7C342B–12 7C342B–15
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Commercial
Military
Industrial
Maximum Static
Current (mA)
Commercial
Military
Industrial
225
12
250
15
250
320
320
225
275
275
7C342B–20
20
250
320
320
225
275
275
7C342B–25
25
250
320
320
225
275
275
7C342B–30
30
250
320
320
225
275
275
7C342B–35
35
250
320
320
225
275
275
Pin Configurations
PLCC
Top View
PGA
BottomView
L
I/O
I/O
INPUT INPUT INPUT
I/O
I/O
I/O
I/O
K
9
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
7C342B
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
C
J
I/O
I/O
I/O
I/O
GND
INPUT
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H
I/O
I/O
I/O
I/O
G
I/O
V
CC
GND
I/O
F
I/O
I/O
7C342B
I/O
I/O
E
I/O
GND
V
CC
I/O
D
I/O
I/O
I/O
I/O
24
45
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344
I/O
I/O
INPUT/
GND
CLK
I/O
I/O
B
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
C342B-2
A
1
I/O
I/O
I/O
I/O
INPUT INPUT INPUT
I/O
I/O
2
3
4
5
6
7
8
9
10
11
C342B-3
2
CY7C342B
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................–65°C to+150°C
Ambient Temperature with
Power Applied....................................................0°C to+70°C
Maximum Junction Temperature
(under bias).................................................................. 150°C
Supply Voltage to Ground Potential ................ –3.0V to+7.0V
Maximum Power Dissipation................................... 2500 mW
DC V
CC
or GND Current ............................................ 500 mA
DC Output Current per Pin........................ –25 mA to+25 mA
DC Input Voltage
[1]
........................................–3.0V to + 7.0V
DC Program Voltage .................................................... 13.0V
Static Discharge Voltage ........................................... >1100V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Commercial
Industrial
Military
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C (Case)
V
CC
5V
±
5%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC1
I
CC2
t
R
t
F
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Output Leakage Current
Output Short Circuit Current
Power Supply Current (Static)
Power Supply Current
[5]
Recommended Input Rise Time
Recommended Input Fall Time
GND < V
IN
< V
CC
V
O
= V
CC
or GND
V
CC
= Max., V
OUT
= 0.5V
[3, 4]
V
I
= GND (No Load)
V
I
= V
CC
or GND (No Load)
f = 1.0 MHz
[4]
Com’l
Mil/Ind
Com’l
Mil/Ind
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–10
–40
–30
Min.
2.4
0.45
V
CC
+0.3
0.8
+10
+40
–90
225
275
250
320
100
100
ns
ns
mA
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2V, f = 1.0 MHz
V
OUT
= 2V, f = 1.0 MHz
Max.
10
10
Unit
pF
pF
Notes:
1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –3.0V for periods less than 20 ns.
2. Typical values are for T
A
= 25°C and V
CC
= 5V.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
4. Guaranteed but not 100% tested.
5. This parameter is measured with device programmed as a 16-bit counter in each LAB.
6. Part (a) in AC Test Load and Waveforms is used for all parameters except t
ER
and t
XZ
, which is used for part (b) in AC Test Load and Waveforms. All external
timing parameters are measured referenced to external pins of the device.
3
CY7C342B
AC Test Loads and Waveforms
[5]
R1 464
Ω
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
250Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
250Ω
3.0V
10%
GND
≤
6 ns
R1 464
Ω
ALL INPUT PULSES
90%
90%
10%
≤
6 ns
C342B-5
C342B-4
(a)
(b)
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT (commercial/military)
163Ω
1.75V
Logic Array Blocks
There are 8 logic array blocks in the CY7C342B. Each LAB
consists of a macrocell array containing 16 macrocells, an ex-
pander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable in-
terconnect array so that they may be accessed by macrocells
in other LABs as well as the macrocells in the LAB in which
they are situated.
Externally, the CY7C342B provides eight dedicated inputs,
one of which may be used as a system clock. There are 52 I/O
pins that may be individually configured for input, output, or
bidirectional data flow.
ment and routing iterations required for a programmable gate
array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C342B may be easily determined
using
Warp2®
or
Warp3®
software by the model shown in
Fig-
ure 1.
The CY7C342B has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
For complete timing information the
Warp3
software provides
a timing simulator.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
datasheet is not implied. Exposure to absolute maximum rat-
ings conditions for extended periods of time may affect device
reliability. The CY7C342B contains circuitry to protect device
pins from high static voltages or electric fields, but normal pre-
cautions should be taken to avoid application of any voltage
higher than the maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND < (V
IN
or V
OUT
) < V
CC
. Unused
inputs must always be tied to an appropriate logic level (ei-
ther V
CC
or GND). Each set of V
CC
and GND pins must be
connected together directly at the device. Power supply de-
coupling capacitors of at least 0.2
µF
must be connected
between VCC and GND. For the most effective decoupling,
each V
CC
pin should be separately decoupled to GND direct-
ly at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types have.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves intercon-
nect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals that may
cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or rac-
es are avoided. The result is ease of design implementation,
often in a signal pass, without the multiple internal logic place-
4
CY7C342B
EXPANDER
DELAY
t
EXP
REGISTER
OUTPUT
DELAY
OUTPUT
t
RD
t
OD
t
XZ
t
ZX
INPUT
INPUT
DELAY
t
IN
LOGIC ARRAY
CONTROL DELAY
t
LAC
LOGIC ARRAY
DELAY
t
LAD
t
CLR
t
PRE
t
RSU
t
RH
t
COMB
t
LATCH
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
t
IC
FEEDBACK
DELAY
t
FD
PIA
DELAY
t
PIA
I/O DELAY
t
IO
C342B-6
Figure 1. CY7C342B Internal Timing Model
5
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