SMM150
Single-Channel Supply Voltage Marginer/Monitor
FEATURES
•
Capable of margining supplies with trim inputs
using either positive or negative trim pin control
•
Wide Margin range from 0.3V to VDD using
internal reference
•
10-bit ADC readout of supply voltage over I
2
C bus
•
Margining Controlled Via:
I
2
C Command
Input Pins (M
UP
, M
DN
)
•
Two programmable general purpose sensor inputs
(COMP1/2) – UV/OV with FAULT Output
•
Programmable glitch filter (COMP1/2)
•
Programmable internal VREF, 0.5V or 1.25V
•
Operates from 2.7V to 5.5V supply
•
General Purpose 256-Byte EEPROM with Write
Protect
•
I
2
C 2-wire serial bus for programming
configuration and monitoring status
•
28 lead QFN
•
20 ball
Ultra
CSP
TM
(Chip-Scale) package
INTRODUCTION
The SMM150 is a highly accurate power supply
voltage supervisor and environmental monitor with
provisions for voltage margining of the monitored supply.
The part includes an internal voltage reference to
accurately monitor and margin the supply to within ±1%.
The SMM150 has the capability to margin over a wide
range from 0.3V to VDD using the internal reference and
can read the value of the supply over the I
2
C bus using
an on-chip 10-bit ADC. The monitor and margin levels
are set using the I
2
C serial bus. The SMM150 initiates
margining via the I
2
C bus or by using the M
UP
or M
DN
inputs. Once the pre-programmed margin target voltage
is reached, the SMM150 holds the converter at this
voltage until receiving an I
2
C command or de-asserting
the margin input pin. When the SMM150 is not
margining, the TRIM output pin is held in a high
impedance state allowing the converter to operate at its
nominal set point. Two general purpose input pins are
provided for sensing under or overvoltage conditions. A
programmable glitch filter associated with these inputs
allows the user to ignore spurious noise signals. A
FAULT# pin is asserted once either input set point is
exceeded.
Using the I
2
C interface, a host system can communicate
with the SMM150 status register and utilize 256-bytes of
nonvolatile memory.
Applications
•
In-system test and control of Point-of-Load (POL)
Power Supplies for Multi-voltage Processors,
DSPs and ASICs
•
Routers, Servers, Storage Area Networks
SIMPLIFIED APPLICATIONS DRAWING
2.7V-5.5V
VDD
GND
VDD_CAP
COMP1
V1
Margin
Commands
Status
Outputs
MUP
MDN
FAULT#
READY
COMP2
SMM150
SDA
SCL
TRIM
TRIM
CAPM
VOUT+
SEN+
I
2
C
Interface
A0
A1
A2
WP
VM
DC-DC Converter
Figure 1 – Applications using the SMM150 Controller to control the Voltage Margining of a DC/DC Converter.
Note: This is an applications example only. Some components and values are not shown.
© SUMMIT
Microelectronics, Inc. 2006 •
757 North Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266
www.summitmicro.com
2075 3.1 01/06/10
1
SMM150
GENERAL DESCRIPTION
The SMM150 is capable of margining the DC output
voltage of LDOs or DC/DC converters that use a
trim/adjust pin. The Margin function is programmable
over a standard 2-wire I
2
C serial data interface and is
used to set the margin low/high DC output voltages.
In margining mode the user communicates with the
SMM150 via the I
2
C serial data bus to select the
desired values for margining. This allows the part to
margin the supplies up or down to these set values
either through asserting the MUP and MDN pins or by
writing to the margin register directly. The margin high
and margin low voltage settings can range from 0.3V
to VDD around the converter’s nominal output voltage
setting depending on the specified margin range of the
DC-DC converter and/or system components, usually
±
10%.
When the SMM150 receives the command to margin,
the TRIM output will begin adjusting the supply to the
selected margin voltage. This is accomplished by
incrementing (or decrementing) an internal counter
based on the digital comparison between the voltage
margin target value and that read by the ADC from the
VM input. This operation is repeated until the 2 values
are equal, after which the SMM150 holds the TRIM
output pin at the voltage required to maintain the
margin setting. An I
2
C command or de-assertion of the
MUP/MDN pin will return the TRIM output pin to a high
impedance state thus allowing the converter to return
to its nominal operating voltage.
The SMM150 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected
to a comparator and compared against the internal
reference (VREF, 0.5V or 1.25V). Each comparator
can be independently programmed to monitor for UV
or OV. When either of the COMP1 or COMP2 inputs
are in fault the open-drain FAULT# output will be
pulled low. A configuration option exists to disable the
FAULT# output during margining.
Programming of the SMM150 is performed over the
industry standard I
2
C 2-wire serial data interface. A
status register is available to read the state of the part
and a Write Protect (WP) pin is available to prevent
writing to the configuration registers and EE memory.
Summit Microelectronics, Inc
2075 3.1 01/06/10
2
SMM150
INTERNAL BLOCK DIAGRAM
READY
FAULT#
VDD
VDD_CAP
GND
VREF
VREF =
1.25V or 0.5V
COMP1
OV/UV
Output
Control
Glitch
Filter
OV/UV
V
REF
COMP2
50kΩ
Up/Dn
MUP
MDN
Margin
Target
Digital
Comparator
Halt
Control
Logic
8-bit DAC
SW1
TRIM
50kΩ
Clock
A0
A1
A2
SCL
SDA
WP
I
2
C
Interface
10Bit
ADC
MUX
SW2
VM
EE
Configuration
Registers
& Memory
CAPM
Figure 2 – SMM150 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pad QFN
Top View
20 Ball
Ultra
CSP
TM
Bottom View
SDA
NC
NC
MDN
MUP
VDD_CAP
NC
Pin 1
SCL
MDN VDD_CAP VDD
Pin 1
28 27 26 25 24 23 22
A1
21
20
A2
SDA
A3
TRIM
A4
COMP1
SCL
A2
NC
A1
READY
A0
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14
GND
SMM150
or
NC
19
18
17
16
15
VDD
TRIM
COMP1
NC
NC
NC
NC
A2
B1
A1
B2
READY
B3
MUP
B4
NC
C1
A0
C2
WP
C3
FAULT#
C4
NC
D1
GND
D2
E2
D3
E3
D4
VM
CAP_M COMP2
WP
NC
CAP_M
FAULT#
COMP2
NC
VM
E1
E4
Summit Microelectronics, Inc
2075 3.1 01/06/10
3
SMM150
PIN DESCRIPTIONS
QFN
Pad
Number
28
1
2
4
6
8
10
20
14
21
23
7
Ultra
CSP
TM
Ball
Number
B2
A1
B1
C1
D1
D2
E2
B3
E4
A4
A3
E1
C3
A2
B4
E3
Pin
Type
I/O
I
I
I
I
I
CAP
O
I
PWR
PWR
GND
I
I
I
I
Pin Name
SDA
SCL
A2
A1
A0
WP
CAPM
TRIM
VM
VDD
VDD_CAP
GND
MUP
MDN
COMP1
COMP2
I
2
C Bi-directional data line
I
2
C clock input.
Pin Description
The address pins are biased either to VDD, GND or left floating. This
allows for a total of 21 distinct device addresses. When
communicating with the SMM150 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.
Programmable Write Protect active high/low input. When asserted,
writes to the configuration registers and general purpose EE are not
allowed. The WP input is internally tied to VDD with a 50KΩ resistor.
External capacitor input used to filter the VM input, 0.02μF.
Output voltage used to control and/or margin converter voltages.
Connect to the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive sense
line or its’ +Vout pin.
Power supply of the part.
External capacitor input used to filter the internal VDD supply rail.
Ground of the part. The SMM150 ground pin should be connected to
the ground of the device under control or to a star point ground. PCB
layout should take into consideration ground drops.
Margin up command input. Asserted high. The MUP input is internally
tied to VDD with a 50KΩ resistor.
Margin down command input. Asserted high. The MDN input is
internally tied to VDD with a 50KΩ resistor.
COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the internally
programmable VREF voltage. Each comparator can be independently
programmed to monitor for UV or OV. The monitor level is set
externally with a resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-
drain FAULT# output will be pulled low. A configuration option exists
to disable the FAULT# output while the device is margining.
Programmable active high/low open drain output indicates that VM is
at its set point. When programmed as an active high output, READY
can also be used as an input. When pulled low, it will latch the state of
the comparator inputs.
No Connect. The bottom side metal plate (Pad 29) can be connected
to GND or left floating.
24
25
19
12
11
D3
O
FAULT#
5
3, 9, 13,
15-18,
22, 26,
27, 29
C2
I/O
READY
C4, D4
NC
NC
Summit Microelectronics, Inc
2075 3.1 01/06/10
4
SMM150
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...................... -55
°
C to 125
°
C
Storage Temperature QFN ................... -65
°
C to 150
°
C
Terminal Voltage with Respect to GND:
VDD Supply Voltage ..........................-0.3V to 6.0V
All Others ................................-0.3V to V
DD
+ 0.7V
FAULT#…………………………….… GND to 15.0V
Output Short Circuit Current ............................... 100mA
Reflow Solder Temperature (10 secs)….………....240
°
C
Junction Temperature.........................…….....…...150°C
ESD Rating per JEDEC……………………..……..2000V
Latch-Up testing per JEDEC………..……......…±100mA
Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial) .......... –40
°
C to +85
°
C
(Commercial).............. 0
°
C to +70
°
C
VDD Supply Voltage.................................. 2.7V to 5.5V
Inputs.........................................................GND to VDD
Package Thermal Resistance (θ
JA
)
28 Pad QFN…………….…………………….…80
o
C/W
20 Ball
Ultra
CSP
TM
………..………….…….…TBD
o
C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
RELIABILITY CHARACTERISTICS
Data Retention……………………………..…..100 Years
Endurance……………………….……….100,000 Cycles
DC OPERATING CHARACTERISTICS
T
A
= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND.
Symbol Parameter
Notes
Min.
Typ.
VDD
VM
I
DD
I
TRIM
V
TRIM
V
ADOC
V
IH
V
IL
V
OL
V
AIH
V
AIL
I
AIT
OV/UV
V
HYST
R
Pull-Up
Supply Voltage
Positive Sense Voltage
Power Supply Current from
VDD
TRIM output current through
100Ω to 1.0V
TRIM output voltage range
Margin Range
Input High Voltage
SDA,SCL,WP,MUP,MDN
Input Low Voltage
SDA,SCL,WP,MUP,MDN
Open Drain Output
FAULT#, READY
Address Input High Voltage,
A2, A1, A0
Address Input Low Voltage,
A2, A1, A0
Address Input Tristate
Maximum Leakage – High Z
Monitor Voltage Range
COMP1/2 DC Hysteresis
Input Pull-Up Resistors
VM pin
TRIM pin floating
TRIM Sourcing Max Current
TRIM Sinking Max Current
I
TRIM
±1.5mA
Depends on Trim range of DC-
DC Converter
VDD = 2.7V
VDD = 5.0V
VDD = 2.7V
VDD = 5.0V
ISINK = 1mA
VDD = 2.7V, R
pullup
≤300kΩ
VDD = 5.0V, R
pullup
≤300kΩ
VDD = 2.7V, R
pulldown
≤300kΩ
VDD = 5.0V, R
pulldown
≤300kΩ
VDD = 2.7V
VDD = 5.0V
COMP1 and COMP2 pins
COMP1 and COMP2 pins,
V
TH
-V
TL
(see Note 1)
See Pin Descriptions
0.9xVDD
0.7xVDD
2.7
0.3
3
1.5
-1.5
GND
0.3
0.9xVDD
0.7xVDD
2.5
VDD
VDD
VDD
0.1xVDD
0.3xVDD
0.2
VDD
VDD
0.1xVDD
0.3xVDD
+3.0
+3.0
VDD
10
50
3.3
Max
5.5
VDD
Unit
V
V
mA
mA
mA
V
V
V
V
V
V
V
μA
V
mV
kΩ
-3.0
-3.0
0
Note 1 – The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting
Threshold Low from Threshold High, V
TH
-V
TL
while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual DC
Hysteresis is derived from the equation: (V
IN
/V
REF
)(Base Hysteresis). For example, if V
IN
=2.5V and V
REF
=1.25V then Actual DC Hysteresis=
(2.5V/1.25V)(0.003V)=6mV.
Summit Microelectronics, Inc
2075 3.1 01/06/10
5
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