ADVANCE
‡
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
36Mb QDR
™
II SRAM
2-WORD BURST
FEATURES
• DLL circuitry for accurate output data placement
MT54W4MH8B
MT54W4MH9B
MT54W2MH18B
MT54W1MH36B
Figure 1
165-Ball FBGA
• Separate independent read and write data ports
with concurrent transactions
• 100 percent bus utilization DDR READ and WRITE
operation
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst counter for low DDR transaction size
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• +1.8V core and HSTL I/O
• Clock-stop capability
• 15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA
package
• User-programmable impedance output
• JTAG boundary scan
VALID PART NUMBERS
PART NUMBER
MT54W4MH8BF-xx
MT54W4MH9BF-xx
MT54W2MH18BF-xx
MT54W1MH36BF-xx
DESCRIPTION
4 Meg x 8, QDRIIb2 FBGA
4 Meg x 9, QDRIIb2 FBGA
2 Meg x 18, QDRIIb2 FBGA
1 Meg x 36, QDRIIb2 FBGA
OPTIONS
• Clock Cycle Timing
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
4 Meg x 8
4 Meg x 9
2 Meg x 18
1 Meg x 36
• Package
165-ball, 15mm x 17mm FBGA
NOTE:
MARKING
1
-4
-5
-6
-7.5
MT54W4MH8B
MT54W4MH9B
MT54W2MH18B
MT54W1MH36B
F
1. A Part Marking Guide for the FBGA devices can be found
on Micron’s Web site—http://www.micron.com/number-
guide.
The Micron
®
QDR™II (Quad Data Rate™) synchro-
nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process.
The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on rising edges of the K and K# input clocks, respec-
tively. Each address location is associated with two
words that burst sequentially into or out of the device.
GENERAL DESCRIPTION
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev. 9/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
GENERAL DESCRIPTION (continued)
Since data can be transferred into and out of the
device on every rising edge of both clocks (K and K#, C
and C#), memory bandwidth is maximized while sys-
tem design is simplified by eliminating bus turn-
arounds.
Depth expansion is accomplished with port selects
for each port (read R#, write W#), which are received at
K rising edge. Port selects permit independent port
operation.
All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest and ending with the highest
address. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
The SRAM operates from a +1.8V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
transactions can remain in operation on both buses
provided that the address rate can be maintained by
the system (2x the clock frequency).
READ cycles are pipelined. The request is initiated
by asserting R# LOW at K rising edge. Data is delivered
after the rising edge of K# (t + 1) using C and C# as the
output timing references or using K and K#, if C and C#
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing
generation. Back-to-back READ cycles are initiated
every K rising edge.
Figure 2
Functional Block Diagram: 2 Meg x 18
n
ADDRESS
R#
W#
K
K#
n
ADDRESS
REGISTRY
& LOGIC
W#
BW0#
BW1#
D (Data In)
R#
K
K#
18
DATA
REGISTRY
& LOGIC
36
WR
R E
I G
T
E 2
WD
R R
I I
T V
E E
R
2
n
x 36
MEMORY
ARRAY
S
E A
NM
S P
E S
36
MUX
RO
E U
G T
P
U
A
T
C
C, C#
or
K, K#
36
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
18
Q
(Data Out)
2
K
CQ, CQ#
(Echo Clock Out)
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for
detailed information. The x8, x9, and x36 operations are the same, with apporpriate adjustments of depth and width.
2. n = 20
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
READ/WRITE OPERATIONS (continued)
WRITE cycles are initiated by W# LOW at K rising
edge. The address for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K that
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and to
provide fully coherent data for all combinations of
reads and writes. A read can immediately follow a
write, even if they are to the same address. Although
the write data has not been written to the memory
array, the SRAM will deliver the data from the write
register instead of using the older data from the mem-
ory array. The latest data is always utilized for all bus
transactions. WRITE cycles can be initiated on every K
rising edge.
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
The QDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175
W
to 350
W
. Alternately, the ZQ ball
can be connected directly to V
DD
Q, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because variations may occur over time in supply volt-
age and temperature. The device samples the value of
RQ. Impedance updates are transparent to the system;
they do not affect device operation, and all data sheet
timing and current specifications are met during an
update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
PARTIAL WRITE OPERATIONS
BYTE WRITE operations are supported, except for
the x8 devices in which nibble write is supported. The
active LOW byte write controls, BWx# (NWx#), are reg-
istered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
Figure 3
Application Example
SRAM #1
Vt
R
D
SA
B
R W W
# # #
ZQ
Q
C C# K K#
R = 250Ω
D
SA
SRAM #4
B
R W W
# # #
ZQ
Q
C C# K K#
R = 250Ω
DATA IN
DATA OUT
Address
Read#
BUS
Write#
MASTER
BW#
R
Vt
Vt
(CPU
or
ASIC)
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
/2
NOTE:
In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets data setup and
hold times at the bus master.
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
CLOCK CONSIDERATIONS
This device utilizes internal delay-locked loops for
maximum output data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
DEPTH EXPANSION
Port select inputs are provided for the read and
write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselecting. Depth expansion requires repli-
cating R# and W# control signals for each bank if it is
desired to have the bank independent of READ and
WRITE operations.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
4 MEG x 8 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NOTE:
1.
2.
3.
4.
5.
Expansion address: 2A for 72Mb
NW1# controls writes to D4:D7
Expansion address: 7A for 144Mb
Expansion address: 5B for 288Mb
NW0# controls writes to D0:D3
2
V
SS
/SA
1
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
SA
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
SA
4
W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
NW1#
2
NC/SA
4
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC/SA
3
NW0#
5
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
京公网安备 11010802033920号
EEWORLD
