HY27UF082G2B-FPIP datasheet, PDF

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HY27UF082G2B-FPIP: DescriptionFlash, 256MX8, 20ns, PBGA63,; Categorystorage storage; File Size406KB，54 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HY27UF082G2B-FPIP Overview

Flash, 256MX8, 20ns, PBGA63,

HY27UF082G2B-FPIP Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SK Hynix
package instruction	FBGA, BGA63,10X12,32
Reach Compliance Code	compliant
Is Samacsys	N
Maximum access time	20 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
JESD-609 code	e3
memory density	2147483648 bit
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	1
Number of departments/size	2K
Number of terminals	63
word count	268435456 words
character code	256000000
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256MX8
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA63,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
page size	2K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	3/3.3 V
Programming voltage	3.3 V
Certification status	Not Qualified
ready/busy	YES
Department size	128K
Maximum standby current	0.00005 A
Maximum slew rate	0.03 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	NAND TYPE
Base Number Matches	1

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HY27UF(08/16)2G2B Series

2Gbit (256Mx8bit) NAND Flash

2Gb NAND FLASH

HY27UF(08/16)2G2B

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.2 / Jan. 2008

HY27UF(08/16)2G2B Series

2Gbit (256Mx8bit) NAND Flash

1.SUMMARY DESCRIPTION

Hynix NAND HY27UF(08/16)2G2B Series have 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 3.3V Vcc

Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid state

mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve

valid data while old data is erased.

The device contains 2048 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typi-

cal 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block.

Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data

input/output as well as command input.

This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of

footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The

on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where

required, and internal verification and margining of data. The modify operations can be locked using the WP input. The

output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple mem-

ories the R/B pins can be connected all together to provide a global status signal.

The copy back function allows the optimization of defective blocks management. When a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error

every 528byte (x8) or 1bit error out of every 264-word (x16) can be detected. Due to this feature, it is no more nor neces-

sary nor recommended to use external 2-bit ECC to detect copy back operation errors. Data read out after copy back read

(both for single and multiplane cases) is allowed.

Even the write-intensive systems can take advantage of the HY27UF(08/16)2G2B Series extended reliability of 100K pro-

gram/erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE

don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a micro-

controller, since the CE transitions do not stop the read operation.

This device includes also extra features like OTP/Unique ID area, Read ID2 extension.

The HY27UF(08/16)2G2B Series are available in 48-TSOP1 12 x 20 mm, 63-FBGA 9 x 11mm, 52-ULGA 12 x 17 mm.

1.1 Product List

PART NUMBER

HY27UF082G2B

HY27UF162G2B

ORGANIZATION

x16

Vcc RANGE

2.7V ~ 3.6V

PACKAGE

48-TSOP1, 63-FBGA, 52-ULGA

48-TSOP1

Rev 0.2 / Jan. 2008

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