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567ABA002531ABG

Description
LVPECL Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size989KB,18 Pages
ManufacturerSilicon Laboratories Inc
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567ABA002531ABG Overview

LVPECL Output Clock Oscillator,

567ABA002531ABG Parametric

Parameter NameAttribute value
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Is SamacsysN
Oscillator typeLVPECL
Base Number Matches1
Ultra Series
Crystal Oscillator (VCXO)
Si567 Data Sheet
Ultra Low Jitter Quad Any-Frequency VCXO (100 fs), 0.2 to
3000 MHz
The Si567 Ultra Series
voltage-controlled crystal oscillator utilizes Silicon Labo-
ratories’ advanced 4
th
generation DSPLL
®
technology to provide an ultra-low jit-
ter, low phase noise clock at four selectable frequencies. The device is factory-
programmed to provide any four selectable frequencies from 0.2 to 3000 MHz
with <1 ppb resolution and maintains exceptionally low jitter for both integer and
fractional frequencies across its operating range. On-chip power supply filtering
provides industry-leading power supply noise rejection, simplifying the task of
generating low jitter clocks in noisy systems that use switched-mode power sup-
plies. Offered in industry-standard 3.2x5 mm and 5x7 mm footprints, the Si567
has a dramatically simplified supply chain that enables Silicon Labs to ship cus-
tom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO,
where a different crystal is required for each output frequency, the Si567 uses
one simple crystal and a DSPLL IC-based approach to provide the desired output
frequencies. The Si567 is factory-configurable for a wide variety of user specifica-
tions, including frequency, output format, and OE pin location/polarity. Specific
configurations are factory-programmed at time of shipment, eliminating the long
lead times associated with custom oscillators.
Pin Assignments
FS1
VC
1
7
6
VDD
KEY FEATURES
• Available with any four selectable frequencies
from 200 kHz to 3000 MHz
• Ultra low jitter: 100 fs RMS typical
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/25G/40G/100G Ethernet
• 56G/112G PAM4 clocking
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• FPGA/ASIC clocking
OE
GND
2
3
8
FS0
(Top View)
5
4
CLK–
CLK+
Pin #
1
2
3
4
5
6
7
8
VC = Voltage Control Pin
Descriptions
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
OE = Output enable
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
FS1 = Frequency Select 1
FS0 = Frequency Select 0
Vc
ADC
Control
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
NVM
Power Supply Regulation
OE, Frequency Select
(Pin Control)
Built-in Power Supply
Noise Rejection
silabs.com
| Building a more connected world.
Rev. 1.0

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567ABA002531ABG 567ABA002531ABGR
Description LVPECL Output Clock Oscillator, LVPECL Output Clock Oscillator,
Maker Silicon Laboratories Inc Silicon Laboratories Inc
Reach Compliance Code unknown unknown
Is Samacsys N N
Oscillator type LVPECL LVPECL
Base Number Matches 1 1
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