MT48LC16M8A2BB-7EAT:G datasheet, PDF

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MT48LC16M8A2BB-7EAT:G: DescriptionSynchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60, 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60; Categorystorage storage; File Size4MB，85 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT48LC16M8A2BB-7EAT:G Overview

Synchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60, 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60

MT48LC16M8A2BB-7EAT:G Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
length	16 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm
Base Number Matches	1

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128Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 Banks

MT48LC16M8A2 – 4 Meg x 8 x 4 Banks

MT48LC8M16A2 – 2 Meg x 16 x 4 Banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths (BL): 1, 2, 4, 8, or full

page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh modes: Standard and low power

(not available on AT devices)

• Auto Refresh

– 64ms, 4096-cycle refresh (commercial and

industrial)

– 16ms, 4096-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Plastic package – OCPL

– 54-pin TSOP II (400 mil)

– 54-pin TSOP II (400 mil) Pb-free

– 60-ball FBGA (8mm x 16mm)

– 60-ball FBGA (8mm x 16mm) Pb-free

– 54-ball VFBGA (x16 only) (8mm x

8mm)

– 54-ball VFBGA (x16 only) (8mm x

8mm) Pb-free

• Timing – cycle time

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

– 6.0ns @ CL = 3 (x16 only)

• Self refresh

– Standard

– Low power

• Revision

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

Notes:

1. Contact Micron for availability.

2. Off-center parting line.

3. Only available on Revision G.

Options

Marking

-75

-7E

-6A

None

:G/:L

None

Options

• Configurations

– 32 Meg x 4 (8 Meg x 4 x 4 banks)

– 16 Meg x 8 (4 Meg x 8 x 4 banks)

– 8 Meg x 16 (2 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = 2 CLK

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-6A

-75

-7E

Clock

Frequency (MHz)

167

133

Marking

32M4

16M8

8M16

Target

RCD-

RP-CL

3-3-3

2-2-2

RCD

(ns)

CL (ns)

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. R 10/12 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ..................................................................................................... 11

Package Dimensions ....................................................................................................................................... 15

Temperature and Thermal Impedance ............................................................................................................ 18

Electrical Specifications .................................................................................................................................. 22

Electrical Specifications – I

Parameters ........................................................................................................ 24

Electrical Specifications – AC Operating Conditions ......................................................................................... 26

Functional Description ................................................................................................................................... 29

Commands .................................................................................................................................................... 30

COMMAND INHIBIT .................................................................................................................................. 30

NO OPERATION (NOP) ............................................................................................................................... 31

LOAD MODE REGISTER (LMR) ................................................................................................................... 31

ACTIVE ...................................................................................................................................................... 31

READ ......................................................................................................................................................... 32

WRITE ....................................................................................................................................................... 33

PRECHARGE .............................................................................................................................................. 34

BURST TERMINATE ................................................................................................................................... 34

REFRESH ................................................................................................................................................... 35

AUTO REFRESH ..................................................................................................................................... 35

SELF REFRESH ....................................................................................................................................... 35

Truth Tables ................................................................................................................................................... 36

Initialization .................................................................................................................................................. 41

Mode Register ................................................................................................................................................ 43

Burst Length .............................................................................................................................................. 45

Burst Type .................................................................................................................................................. 45

CAS Latency ............................................................................................................................................... 47

Operating Mode ......................................................................................................................................... 47

Write Burst Mode ....................................................................................................................................... 47

Bank/Row Activation ...................................................................................................................................... 48

READ Operation ............................................................................................................................................. 49

WRITE Operation ........................................................................................................................................... 58

Burst Read/Single Write .............................................................................................................................. 65

PRECHARGE Operation .................................................................................................................................. 66

Auto Precharge ........................................................................................................................................... 66

AUTO REFRESH Operation ............................................................................................................................. 78

SELF REFRESH Operation ............................................................................................................................... 80

Power-Down .................................................................................................................................................. 82

Clock Suspend ............................................................................................................................................... 83

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. R 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 32 Meg x 4 Functional Block Diagram ................................................................................................. 8

Figure 2: 16 Meg x 8 Functional Block Diagram ................................................................................................. 9

Figure 3: 8 Meg x 16 Functional Block Diagram ............................................................................................... 10

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11

Figure 5: 60-Ball FBGA (TopView) .................................................................................................................. 12

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13

Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 15

Figure 8: 60-Ball FBGA (x8 Device), 8mm x 16mm – Package Code FB/BB ........................................................ 16

Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4 ....................................................... 17

Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 20

Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21

Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 21

Figure 13: ACTIVE Command ........................................................................................................................ 31

Figure 14: READ Command ........................................................................................................................... 32

Figure 15: WRITE Command ......................................................................................................................... 33

Figure 16: PRECHARGE Command ................................................................................................................ 34

Figure 17: Initialize and Load Mode Register .................................................................................................. 42

Figure 18: Mode Register Definition ............................................................................................................... 44

Figure 19: CAS Latency .................................................................................................................................. 47

Figure 20: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 48

Figure 21: Consecutive READ Bursts .............................................................................................................. 50

Figure 22: Random READ Accesses ................................................................................................................ 51

Figure 23: READ-to-WRITE ............................................................................................................................ 52

Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 53

Figure 25: READ-to-PRECHARGE .................................................................................................................. 53

Figure 26: Terminating a READ Burst ............................................................................................................. 54

Figure 27: Alternating Bank Read Accesses ..................................................................................................... 55

Figure 28: READ Continuous Page Burst ......................................................................................................... 56

Figure 29: READ – DQM Operation ................................................................................................................ 57

Figure 30: WRITE Burst ................................................................................................................................. 58

Figure 31: WRITE-to-WRITE .......................................................................................................................... 59

Figure 32: Random WRITE Cycles .................................................................................................................. 60

Figure 33: WRITE-to-READ ............................................................................................................................ 60

Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 61

Figure 35: Terminating a WRITE Burst ............................................................................................................ 62

Figure 36: Alternating Bank Write Accesses ..................................................................................................... 63

Figure 37: WRITE – Continuous Page Burst ..................................................................................................... 64

Figure 38: WRITE – DQM Operation ............................................................................................................... 65

Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 67

Figure 40: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 68

Figure 41: READ With Auto Precharge ............................................................................................................ 69

Figure 42: READ Without Auto Precharge ....................................................................................................... 70

Figure 43: Single READ With Auto Precharge .................................................................................................. 71

Figure 44: Single READ Without Auto Precharge ............................................................................................. 72

Figure 45: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 73

Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 73

Figure 47: WRITE With Auto Precharge ........................................................................................................... 74

Figure 48: WRITE Without Auto Precharge ..................................................................................................... 75

Figure 49: Single WRITE With Auto Precharge ................................................................................................. 76

Figure 50: Single WRITE Without Auto Precharge ............................................................................................ 77

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. R 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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