CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Electrical Specifications
Parameters with MIN and/or MAX limits are 100% tested at +25°C, V+ = 0V unless otherwise specified.
Temperature limits established by characterization and are not production tested.
ICL7667C, M
T
A
= +25°C
ICL7667M
0°C
T
A
+70°C
MAX
MIN
TYP
MAX
UNITS
PARAMETER
DC SPECIFICATIONS
Logic 1 Input Voltage
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic 0 Input Voltage
Input Current
Output Voltage High
Output Voltage Low
Output Resistance
Output Resistance
Power Supply Current
Power Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP
V
IH
V
IH
V
IL
V
IL
I
IL
V
OH
V
OL
R
OUT
R
OUT
I
CC
I
CC
V+ = 4.5V
V+V+ = 15V
V+ = 4.5V
V+ = 15V
V+ = 15V, V
IN
= 0V and 15V
V+ = 4.5V and 15V
V+ = 4.5V and 15V
V
IN
= V
IL
, I
OUT
= -10mA, V+ = 15V
V
IN
= V
IH
, I
OUT
= 10mA, V+ = 15V
V+ = 15V, V
IN
= 3V both inputs
V+ = 15V, V
IN
= 0V both inputs
2.0
2.0
-
-
-0.1
V+ -0.05
-
-
-
-
-
-
-
-
-
-
V+
0
7
8
5
150
-
-
0.8
0.8
0.1
-
0.05
10
12
7
400
2.0
2.0
-
-
-0.1
V+ -0.1
-
-
-
-
-
-
-
-
-
-
V+
-
-
-
-
-
-
-
0.5
0.5
0.1
-
0.1
12
13
8
400
V
V
V
V
µA
V
V
mA
µA
SWITCHING SPECIFICATIONS
Delay Time
Rise Time
Fall Time
Delay Time
T
D2
T
R
T
F
T
D1
(Figure 3)
(Figure 3)
(Figure 3)
(Figure 3)
-
-
-
-
35
20
20
20
50
30
30
30
-
-
-
-
-
-
-
-
60
40
40
40
ns
ns
ns
ns
FN2853 Rev 7.01
Feb 11, 2020
Page 2 of 11
ICL7667
Test Circuits
V+ = 15V
+5V
+
4.7
µ
F
INPUT
ICL7667
INPUT RISE AND
FALL TIMES
10ns
INPUT
0.1
µ
F
10%
90%
0.4V
OUTPUT
C
L
= 1000pF
15V
T
D1
t
f
90%
T
D2
t
r
90%
OUTPUT
0V
10%
10%
Typical Performance Curves
1µs
V+ = 15V
100
90
80
100
t
r
AND t
f
(ns)
t
RISE
10
t
FALL
1
10
100
1000
C
L
(pF)
10k
100k
T
D1
AND T
D2
(ns)
70
60
50
40
30
20
10
0
-55
0
25
70
TEMPERATURE (°C)
125
T
D1
T
D2
C
L
= 1nF
V+ = 15V
FIGURE 1. RISE AND FALL TIMES vs C
L
50
C
L
= 1nF
V+ = 15V
t
r
AND t
f
t
r
AND t
f
(ns)
30
I
V+
(mA)
10
30
FIGURE 2. T
D1
, T
D2
vs TEMPERATURE
V+ = 15V
200kHz
40
20kHz
20
3.0
10
0
-55
0
25
70
125
TEMPERATURE (°C)
1.0
10
100
1k
C
L
(pF)
10k
100k
FIGURE 3. t
r
, t
f
vs TEMPERATURE
FIGURE 4. I
V+
vs C
L
FN2853 Rev 7.01
Feb 11, 2020
Page 3 of 11
ICL7667
Typical Performance Curves
(Continued)
100
100
I
V+
(mA)
I
V+
(mA)
V+ = 15V
10
V+ = 5V
1
10
V+ = 15V
1
C
L
= 1nF
100k
1M
10M
100mA
10k
100k
V+ = 5V
C
L
= 10pF
1M
10M
100µA
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. I
V+
vs FREQUENCY
50
50
FIGURE 6. NO LOAD I
V+
vs FREQUENCY
40
40
t
r
AND t
D2
(ns)
t
D1
AND t
f
(ns)
30
t
f
20
t
D1
10
C
L
= 1nF
0
5
10
V+ (V)
15
30
t
r
= T
D2
20
10
C
L
= 10pF
0
5
10
V+ (V)
15
FIGURE 7. DELAY AND FALL TIMES vs V+
FIGURE 8. RISE TIME vs V+
Detailed Description
The ICL7667 is a dual high-power CMOS inverter whose
inputs respond to TTL levels while the outputs can swing as
high as 15V. Its high output current enables it to rapidly charge
and discharge the gate capacitance of power MOSFETs,
minimizing the switching losses in switchmode power supplies.
Since the output stage is CMOS, the output will swing to within
millivolts of both V- and V+ without any external parts or extra
power supplies as required by the DS0026/56 family. Although
most specifications are at
V+ = 15V, the propagation delays and specifications are almost
independent of V+.
In addition to power MOS drivers, the ICL7667 is well suited for
other applications such as bus, control signal, and clock
drivers on large memory of microprocessor boards, where the
load capacitance is large and low propagation delays are
required. Other potential applications include peripheral power
drivers and charge-pump voltage inverters.
Input Stage
The input stage is a large N-Channel FET with a P-Channel
constant-current source. This circuit has a threshold of about
1.5V, relatively independent of the V+ voltage. This means that
the inputs will be directly compatible with TTL over the entire
4.5V - 15V V+ range. Being CMOS, the inputs draw less than
1µA of current over the entire input voltage range of V- to V+.
The quiescent current or no load supply current of the ICL7667
is affected by the input voltage, going to nearly zero when the
inputs are at the 0 logic level and rising to 7mA maximum when
both inputs are at the 1 logic level. A small amount of
hysteresis, about 50mV to 100mV at the input, is generated by
positive feedback around the second stage.
Output Stage
The ICL7667 output is a high-power CMOS inverter, swinging
between V- and V+. At V+ = 15V, the output impedance of the
inverter is typically 7Ω. The high peak current capability of the
ICL7667 enables it to drive a 1000pF load with a rise time of
FN2853 Rev 7.01
Feb 11, 2020
Page 4 of 11
ICL7667
only 40ns. Because the output stage impedance is very low, up
to 300mA will flow through the series N-Channel and P-
Channel output devices (from V+ to V-) during output transitions.
This crossover current is responsible for a significant portion of
the internal power dissipation of the ICL7667 at high frequencies.
It can be minimized by keeping the rise and fall times of the input
to the ICL7667 below 1µs.
As noted above, the input inverter current is input voltage
dependent, with an I
V+
of 0.1mA maximum with a logic 0 input
and 6mA maximum with a logic 1 input.
The output stage crowbar current is the current that flows
through the series N-Channel and P-Channel devices that form
the output. This current, about 300mA, occurs only during
output transitions.
Caution:
The inputs should never be
allowed to remain between V
IL
and V
IH
since this could leave
the output stage in a high current mode, rapidly leading to
destruction of the device. If only one of the drivers is being
used, be sure to tie the unused input to V- or ground.
NEVER
leave an input floating. The average supply current drawn by
the output stage is frequency dependent, as can be seen in
Figure 5 (I
V+
vs Frequency graph in the Typical Characteristics
Graphs).
The output stage I
2
R power dissipation is nothing more than
the product of the output current times the voltage drop across
the output device. In addition to the current drawn by any
resistive load, there will be an output current due to the
charging and discharging of the load capacitance. In most high
frequency circuits the current used to charge and discharge
capacitance dominates, and the power dissipation is
approximately:
P
AC
=
CV
V
2
f
(EQ. 1)
Application Notes
Although the ICL7667 is simply a dual level-shifting inverter,
there are several areas to which careful attention must be paid.
Grounding
Since the input and the high current output current paths both
include the V- pin, it is very important to minimize and common
impedance in the ground return. Since the ICL7667 is an
inverter, any common impedance will generate negative
feedback, and will degrade the delay, rise and fall times. Use a
ground plane if possible, or use separate ground returns for the
input and output circuits. To minimize any common inductance
in the ground return, separate the input and output circuit
ground returns as close to the ICL7667 as is possible.
Bypassing
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.7µF tantalum
capacitor in parallel with a low inductance 0.1µF capacitor is
usually sufficient bypassing.
where C = Load Capacitance, f = Frequency
In cases where the load is a power MOSFET and the gate
drive requirement are described in terms of gate charge, the
ICL7667 power dissipation will be:
P
AC
=
QGV
V
f
(EQ. 2)
Output Damping
Ringing is a common problem in any circuit with very fast rise
or fall times. Such ringing will be aggravated by long inductive
lines with capacitive loads. Techniques to reduce ringing
include:
• Reduce inductance by making printed circuit board traces as
short as possible.
• Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
• Use a 10Ω to 30Ω resistor in series with the output of the
ICL7667. Although this reduces ringing, it will also slightly
increase the rise and fall times.
• Use good by-passing techniques to prevent supply
voltage ringing.
where Q
G
= Charge required to switch the gate, in Coulombs,
f = Frequency.
Power MOS Driver Circuits
Power MOS Driver Requirements
Because it has a very high peak current output, the ICL7667
the at driving the gate of power MOS devices. The high current
output is important since it minimizes the time the power MOS
device is in the linear region. Figure 9 is a typical curve of
Charge vs Gate voltage for a power MOSFET. The flat region
is caused by the Miller capacitance, where the drain-to-gate
capacitance is multiplied by the voltage gain of the FET. This
increase in capacitance occurs while the power MOSFET is in
the linear region and is dissipating significant amounts of
power. The very high current output of the ICL7667 is able to
rapidly overcome this high capacitance and quickly turns the
MOSFET fully on or off.
Power Dissipation
The power dissipation of the ICL7667 has three main
components:
1. Input inverter current loss
2. Output stage crossover current loss
3. Output stage I
2
R power loss
The sum of the above must stay within the specified limits for
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