CS5522/24/28
2-, 4-, or 8-Channel, 24-Bit
∆Σ
Multi-Range ADC
Features
General Description
The 24-bit CS5522/24/28 are highly integrated
∆Σ
A/D con-
verters which include an instrumentation amplifier, a PGA
(programmable gain amplifier), a multi-channel multiplexer,
digital filters, and self and system calibration circuitry.
The chips are designed to provide their own negative
supply which enables their on-chip instrumentation am-
plifiers to measure bipolar ground-referenced signals
≤±100
mV. By directly supplying NBV with -2.5 V and
with VA+ at 5 V,
±
2.5 V signals (with respect to ground)
can be measured.
The digital filters provide programmable output update
rates of 3.76 Hz, 7.5 Hz, 15 Hz, 30 Hz, 60 Hz, 123 Hz,
169 Hz, and 202 Hz when operating from a 32 kHz crys-
tal. The CS5522/24/28 are capable of producing output
update rates up to 606 Hz with a 100kHz clock. The fil-
ters are designed to settle to full accuracy for the
selected output update rate within one conversion cycle.
When operated at word rates of 15 Hz or less, the digital
filters reject both 50 and 60 Hz line interference
±
3 Hz
simultaneously.
Low power, single conversion settling time, programma-
ble output rates, and the ability to handle negative input
signals make these single supply products ideal solu-
tions for isolated and non-isolated applications.
ORDERING INFORMATION
See page 32.
VREF+ VREF-
Differential
4th Order
∆Σ
Modulator
DGND VD+
Digital Filter
l
Delta-Sigma A/D Converter
l
Bipolar/Unipolar Input Ranges
l
Chopper Stabilized Instrumentation Amplifier
l
On-Chip Charge Pump Drive Circuitry
l
Multiplexer
l
Conversion Data FIFO
l
2-Bit Output Latch
l
Simple three-wire serial interface
l
Output Settles in One Conversion Cycle
l
50/60 Hz Simultaneous Rejection
l
+5 V Voltage Reference Input Capability
l
System and Self-Calibration with R/W
Registers per Channel
l
Single +5 V Analog Supply
+3.0 V or +5 V Digital Supply
l
Programmable Channel Sequencer
l
Low Power Mode Consumption: 4 mW
VA+
AIN1+
AIN1-
AIN2+
AIN2-
AGND
-
Linearity Error: 0.0007%FS
-
Noise Free Resolution: 18-bits
-
25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
-
SPI™ and Microwire™ Compatible
-
Schmitt Trigger on Serial Clock (SCLK)
M
U
X
CS5522
shown
+
X20
-
Programmable
Gain
Calibration
Register
Control
Register
Output
Register
CS
SCLK
SDI
SDO
NBV
CPD
Latch
A0 A1
Calibration
Memory
Calibration
µC
Clock
Gen.
XIN XOUT
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 1998
(All Rights Reserved)
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
JAN ‘98
DS265PP1
1
CS5522/24/28
(T
A
= 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,
NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = ±100 mV;
See Notes 1 and 2.)
Parameter
Min
-
24
(Note 3)
(Note 3)
(Notes 3 and 4)
-
-
-
-
-
(Note 4)
-
1
-
-
-
(Note 5)
-
Typ
Max
Unit
%FS
Bits
LSB
24
LSB
24
nV/°C
ppm
ppm
ppm/°C
V
dB
dB
pF
µA/V
ANALOG CHARACTERISTICS
Accuracy
Linearity Error
No Missing Codes
Bipolar Offset
Unipolar Offset
Offset Drift
Bipolar Gain Error
Unipolar Gain Error
Gain Drift
±0.0007 ±0.0015
-
±16
±32
20
±8
±16
1
2.5
110
130
16
0.6
-
±32
±64
-
±31
±62
3
VA+
-
-
-
-
Voltage Reference Input
Range
(VREF+) - (VREF-)
Common Mode Rejection dc
50, 60 Hz
Input Capacitance
CVF Current
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specifications guaranteed by design, characterization, and/or test.
3. Specification applies to the device only and does not include any effects by external parasitic
thermocouples.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
5. See the section of the data sheet which discusses input models.
RMS NOISE
(Notes 6 and 7)
Output Rate -3 dB Filter
(Hz)
Frequency
3.76
3.27
7.51
6.55
15.0
12.7
30.1
25.4
60.0
50.4
123.2 (Note 8)
103.6
168.9 (Note 8)
141.3
202.3 (Note 8)
169.2
25 mV
90 nV
110 nV
170 nV
250 nV
500 nV
2.0 µV
10 µV
30 µV
Input Range, (Bipolar/Unipolar Mode)
55 mV
100 mV
1V
2.5 V
90 nV
130 nV
1.0 µV
2.0 µV
130 nV
190 nV
1.5 µV
3.0 µV
200 nV
250 nV
2.0 µV
5.0 µV
300 nV
500 nV
4.0 µV
10 µV
1.0 µV
1.5 µV
15 µV
45 µV
4.0 µV
8.0 µV
72 µV
190 µV
20.0 µV
30 µV
340 µV
900 µV
55 µV
105 µV
1.1 mV
2.4 mV
5V
4.0 µV
7 µV
10 µV
15 µV
85 µV
350 µV
2.0 mV
5.3 mV
Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.
7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.
8. For input ranges <100 mV and output rates >60 Hz, 32.768 kHz chopping frequency is used.
Specifications are subject to change without notice.
2
DS265PP1
CS5522/24/28
ANALOG CHARACTERISTICS
(Continued)
Parameter
Min
Typ
Max
Unit
Analog Input
Common Mode + Signal on AIN+ or AIN-
Bipolar/Unipolar Mode
NBV = -1.8 to -2.5 V
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
NBV = AGND
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
Common Mode Rejection dc
50, 60 Hz
Input Capacitance
CVF Current on AIN+ or AIN-
(Note 5)
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
System Calibration Specifications
Full Scale Calibration Range
Bipolar/Unipolar Mode
25 mV
55 mV
100 mV
1V
2.5 V
5V
Offset Calibration Range
Bipolar/Unipolar Mode
25 mV
55 mV
100 mV
(Note 9)
1V
2.5 V
5V
Power Supplies
DC Power Supply Currents (Normal Mode)
I
A+
I
D+
I
NBV
Power Consumption
Normal Mode
Low Power Mode
Standby
Sleep
dc Positive Supplies
dc NBV
(Note 10)
-0.150
NBV
1.85
0.0
-
-
-
-
-
-
-
-
-
120
120
10
100
1.2
0.950
VA+
2.65
VA+
-
-
-
300
-
V
V
V
V
dB
dB
pF
pA
µA/V
17.5
38.5
70
0.70
1.75
3.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.3
15
400
7.5
4.0
1.2
500
95
110
32.5
71.5
105
1.30
3.25
VA+
±12.5
±27.5
±50
±0.5
±1.25
±2.50
1.7
30
550
10
6.5
-
-
-
-
mV
mV
mV
V
V
V
mV
mV
mV
V
V
V
mA
µA
µA
mW
mW
mW
µW
dB
dB
Power Supply Rejection
Notes: 9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path.
10. All outputs unloaded. All input CMOS levels.
DS265PP1
3
CS5522/24/28
5 V DIGITAL CHARACTERISTICS
(T
A
= 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;
See Notes 2 and 11.))
Parameter
High-Level Input Voltage
All Pins Except XIN and SCLK
XIN
SCLK
All Pins Except XIN and SCLK
XIN
SCLK
Symbol
V
IH
Min
0.6 VD+
(VD+)-0.5
(VD+) - 0.45
-
0.0
-
(VA+) - 1.0
(VD+) - 1.0
(VD+) - 1.0
V
OL
-
-
-
I
in
I
OZ
C
out
-
-
-
-
-
-
±1
-
9
0.4
0.4
0.4
±10
±10
-
V
V
V
µA
µA
pF
Typ
-
-
-
-
-
-
-
-
-
Max
-
VD+
-
0.8
1.5
0.6
-
-
-
Unit
V
V
V
V
V
V
V
V
V
Low-Level Input Voltage
V
IL
High-Level Output Voltage
All Pins Except CPD and SDO (Note 12)
CPD, I
out
= -4.0 mA
SDO, I
out
= -5.0 mA
Low-Level Output Voltage
All Pins Except CPD and SDO, I
out
= 1.6 mA
CPD, I
out
= 2 mA
SDO, I
out
= 5.0 mA
Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance
Notes: 11. All measurements performed under static conditions.
V
OH
12. I
out
= -100 µA unless stated otherwise. (V
OH
= 2.4 V @ I
out
= -40 µA.)
3.0 V DIGITAL CHARACTERISTICS
See Notes 2 and 11.))
Parameter
High-Level Input Voltage
(T
A
= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;
Symbol
V
IH
Min
0.6 VD+
(VD+)-0.5
(VD+) - 0.45
-
0.0
-
(VA+) - 0.3
(VD+) - 1.0
(VD+) - 1.0
V
OL
-
-
-
I
in
I
OZ
C
out
-
-
-
-
-
-
±1
-
9
0.3
0.4
0.4
±10
±10
-
V
V
V
µA
µA
pF
Typ
-
-
-
-
-
-
-
-
-
Max
-
VD+
-
0.16 VD+
0.3
0.6
-
-
-
Unit
V
V
V
V
V
V
V
V
V
All Pins Except XIN and SCLK
XIN
SCLK
All Pins Except XIN and SCLK
XIN
SCLK
Low-Level Input Voltage
V
IL
High-Level Output Voltage
All Pins Except CPD and SDO, I
out
= -400 µA
CPD, I
out
= -4.0 mA
SDO, I
out
= -5.0 mA
Low-Level Output Voltage
All Pins Except CPD and SDO, I
out
= 400 µA
CPD, I
out
= 2 mA
SDO, I
out
= 5.0 mA
Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance
V
OH
4
DS265PP1
CS5522/24/28
DYNAMIC CHARACTERISTICS
Parameter
Modulator Sampling Frequency
Filter Settling Time to 1/2 LSB (Full Scale Step)
Symbol
f
s
t
s
Ratio
XIN/2
1/f
out
Unit
Hz
s
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V; See Note 13.))
Parameter
DC Power Supplies
Analog Reference Voltage
Negative Bias Voltage
Notes: 13. All voltages with respect to ground.
Positive Digital
Positive Analog
(VREF+) - (VREF-)
Symbol
VD+
VA+
VRef
diff
NBV
Min
2.7
4.75
1.0
-1.8
Typ
5.0
5.0
2.5
-2.1
Max
5.25
5.25
VA+
-2.5
Unit
V
V
V
V
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0 V; See Note 13.)
Parameter
DC Power Supplies
(Note 14)
Positive Digital
Positive Analog
Negative Potential
(Note 15 and 16)
(Note 17)
VREF pins
AIN Pins
Symbol
VD+
VA+
NBV
I
IN
I
OUT
PDN
V
INR
V
INA
V
IND
T
A
T
stg
Min
-0.3
-0.3
+0.3
-
-
-
NBV - 0.3
NBV - 0.3
-0.3
-40
-65
Typ
-
-
-2.1
-
-
-
-
-
-
-
-
Max
+6.0
+6.0
-3.0
±10
±25
500
(VA+) + 0.3
(VA+) + 0.3
(VD+) + 0.3
85
150
Unit
V
V
V
mA
mA
mW
V
V
V
°C
°C
Negative Bias Voltage
Input Current, Any Pin Except Supplies
Output Current
Power Dissipation
Analog Input Voltage
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Notes: 14. No pin should go more negative than NBV - 0.3 V.
15. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
16. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
17. Total power dissipation, including all input currents and output currents.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS265PP1
5
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