MR82C52/B datasheet, PDF - EEWORLD Datasheet

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MR82C52/B: Description1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CQCC28; Categorysemiconductor The embedded processor and controller; File Size987KB，21 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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MR82C52/B Overview

1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CQCC28

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DATASHEET

82C52

CMOS Serial Controller Interface

The Intersil 82C52 is a high performance programmable

Universal Asynchronous Receiver/Transmitter (UART) and

Baud Rate Generator (BRG) on a single chip. Utilizing the

Intersil advanced Scaled SAJI IV CMOS process, the 82C52

will support data rates up to 1M baud asynchronously with a

16X clock (16MHz clock frequency).

The on-chip Baud Rate Generator can be programmed for any

one of 72 different baud rates using a single industry standard

crystal or external frequency source. A unique pre-scale divide

circuit has been designed to provide standard RS-232-C baud

rates when using any one of three industry standard crystals

(1.8432MHz, 2.4576MHz, or 3.072MHz).

A programmable buffered clock output (CO) is available and

can be programmed to provide either a buffered oscillator or

16X baud rate clock for general purpose system usage.

FN2950

Rev 4.00

November 25, 2015

Features

• Single Chip UART/BRG

• DC to 16MHz (1M Baud) Operation

• Crystal or External Clock Input

• On-Chip Baud Rate Generator - 72 Selectable Baud Rates

• Interrupt Mode with Mask Capability

• Microprocessor Bus Oriented Interface

• 80C86 Compatible

• Single +5V Power Supply

• Low Power Operation . . . . . . . . . . . . . . . . . . . . 1mA/MHz Typ

• Modem Interface

• Line Break Generation and Detection

• Operating Temperature Range:

- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C

- I82C52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

- M82C52. . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

• Pb-Free Plus Anneal Available (RoHS Compliant)

•

Ordering Information

1M BAUD

PART MARKING

TEMP

RANGE (°C)

0 to +70

PDIP

PACKAGE

PKG. DWG. #

E28.6

CP82C52

(No longer available or supported

Recommended Replacement:

CP82C52Z)

CP82C52Z (Note)

IP82C52

CS82C5296

CS82C52Z*

(Note)

IS82C52

IS82C52Z*

(Note)

ID82C52

MD82C52/B

8501501XA

MR82C52/B

85015013A

*Add "96" suffix for tape and reel.

85015013A

CP82C52Z

IP82C52

CS82C52

CS82C52Z

IS82C52

IS82C52Z

ID82C52

MD82C52/B

8501501XA

0 to +70

-40 to +85

0 to +70

0to +70

-40 to +85

-55 to +125

PDIP (Pb-Free)**

PDIP

PLCC (Tape & Reel)

PLCC

(Pb-Free)

PLCC

(Pb-Free)

CERDIP

E28.6

N28.45

F28.6

SMD#

-55 to +125

CLCC

SMD#

F28.6

J28.A

**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN2950 Rev 4.00

November 25, 2015

Page 1 of 21

82C52

Pin Description

SYMBOL

D0-D7

NO.

3-10

TYPE

I/O

ACTIVE

LEVEL

Low

High

DESCRIPTION

READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data output

depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.

WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52. Addressing

and chip select action is the same as for read operations.

DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data,

control and status information between the 82C52 and the CPU. For character formats of less than 8

bits, the corresponding D7, D6 and D5 are considered “don't cares” for data WRITE operations and

are 0 for data READ operations. These lines are normally in a high impedance state except during

read operations. D0 is the Least Significant Bit (LSB) and is the first serial data bit to be received or

transmitted.

ADDRESS INPUTS: The address lines select the various internal registers during CPU bus

operations.

CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be used

as an external clock input in which case OX should be left open.

High

SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is a logic

one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when CTS is false,

when RST is true, when the Transmitter Register is empty, or when in the Loop Mode.

GROUND: Power supply ground connection.

CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem Status

false level on CTS will inhibit transmission of data on the SD0 output and will hold SD0 in the Mark

(high) state. If CTS goes false during transmission, the current character being transmitted will be

completed. CTS does not affect Loop Mode operation.

DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register. Any

change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state of this signal

does not affect any other circuitry within the 82C52.

DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appropriate bit

in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic 0 in the DTR bit

in the MCR or whenever a reset (RST = high) is applied to the 82C52.

REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate bit in

the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or whenever a

reset (RST = high) is applied to the 82C52.

CLOCK OUT: This output is user programmable to provide either a buffered IX output or a buffered

Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock source) output is

provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero. Writing a logic one to

BRSR bit 7 causes the CO output to provide a buffered version of the internal Baud Rate Generator

clock which operates at sixteen times the programmed baud rate. On reset D7 (CO select) is reset to

High

TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the

Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application of a

reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever data is

written to the TBR.

RESET: The RST input forces the 82C52 into an “Idle” mode in which all serial data activities are

suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The

UART Status Register (USR) is cleared except for the TBRE and TC bits, which are set. The 82C52

remains in an “Idle” state until programmed to resume serial data activities. The RST input is a

Schmitt triggered input.

INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control

INTR logic. Figure 9 in Design Information shows the overall relationship of these interrupt control

signals.

A0, A1

IX, OX

SDO

11, 12

13, 14

I/O

High

GND

CTS

Low

DSR

Low

DTR

Low

RTS

Low

TBRE

RST

High

INTR

High

FN2950 Rev 4.00

November 25, 2015

Page 3 of 21

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