áç
APRIL 2002
PRELIMINARY
XRT95L34
REV. P1.0.1
OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S
GENERAL DESCRIPTION
The XRT95L34 is an OC-12/STM-4, Quad OC-3/
STM-1 POS/ATM Framer with integrated CDR’s. ATM
direct mapping and cell delineation are supported, so
are packets (PPP) over SONET for POS mapping
and frame processing. The XRT95L34 contains an in-
tegral SONET framer which provides framing and er-
ror accumulation in accordance with ANSI/ITU-T
specifications. The configuration of this device is
through internal registers accessible via an 8-bit par-
allel, memory mapped, microprocessor interface.
APPLICATIONS
•
Edge and WAN ATM Switches
•
IP Routers, Packet Switches and Hubs
•
Multi-protocol Switches
FEATURES
•
A single chip solution for ATM UNI and packet over
SONET
•
Provides the highest level of protection switching
flexibility for up to 1:14 protected OC-3/STM-1
ports.
•
Provides quad serial OC-3/STM-1 interfaces with
integrated CDR, compatible with industry standard
optical modules.
•
Provides serial OC-12/STM-4 interfaces with inte-
grated CDR, compatible with industry standard
optical modules.
•
Supports the mappings for any standard combina-
tion of STS-12c/AU-4c or STS-3c/AU4.
•
Provides four 8-bit busses on the line side running
at 19.44 MHz to connect OC-12 framers through a
parallel interface or aggregate four low speed OC-3
devices into an OC-12 line.
•
Supports both SONET and SDH on all interfaces.
SONET/SDH is programmable per interface.
•
Terminates Section Overhead, Line Overhead and
STS-Path Overhead on 4xOC-3, 1xOC-12 inter-
faces. Supports performance monitoring and
alarms required by GR.253, G.707 and ANSI
T1.105.
•
Provides SONET frame scrambling and de-scram-
bling.
•
Offers differential line interfaces.
•
Offers multiple microprocessor compatible interface
- Intel, Motorola, PowerPC, Mips.
•
Provides 8/16-bit data UTOPIA level II/III Interface
and POS interface.
•
Includes ATM cell or PPP packet Mapping.
•
Utilizes a single +3.3V power supply with +5V input
tolerance.
•
Offered in a 584-pin TBGA package.
SONET TRANSMITTER
•
Performs standard OC-3c/STM-1c transmit pro-
cessing.
•
Conforms to ITU-T I.432, ANSI T1.105, and
Bellcore-253.
•
Performs SONET frame insertion and accepts
external frame synchronization.
•
Performs optional transmit data scrambling.
•
Performs POH, TOH generation/insertion.
•
Generates transmit payload pointer (H1, H2) (fixed
at 522) with NDF insertion.
•
Inserts A1/A2 with optional error mask.
•
Computes and inserts BIP-8 (B1, B2) with optional
error mask.
•
Generates AIS-L, REI-L and RDI-L according to
receiver state with option of SW/HW insertion.
•
Inserts LOS, forces SEF by software.
•
Generates RDI-P and REI-P automatically with
optional SW/HW override.
•
Inserts fixed-stuff columns, calculates and inserts
B3 error code.
•
Performs mapping for ATM cells and PPP packets
into the SDH SPE/VC.
SONET RECEIVER
•
Performs standard STS-12/STS-3c/STM-1c receive
processing.
•
Conforms to ITU-T I.432, ANSI T1.105, and
Bellcore-253.
•
Provides fully programmable threshold detection for
SD and SF condition.
•
Provides 155.52 MHz 16-bit parallel interface.
•
Provides section trace buffer with mismatch detec-
tion and invalid message detection.
•
Performs SONET frame synchronization.
•
Supports NDF, positive stuff and negative stuff for
pointer processor.
•
Performs receive data de-scrambling.
•
Performs POH, TOH interpretation/extraction.
•
Interprets payload pointer (H1, H2).
•
Extracts data communication channels from D1-D3
and D4-D12.
•
Detects Out Of Frame (OOF), Loss Of Frame
(LOF), Loss Of Signal (LOS), APS failure.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT95L34
OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S
REV. P1.0.1
áç
PRELIMINARY
•
Detects Line Alarm Indication (L-AIS), Line remote
Defect Indication (L-RDI), Loss Of Pointer.
•
Detects Path Alarm Indication, Path remote Defect
Indication, Path extended RDI.
•
Provides signal label monitor with PLM detection.
•
Supports path trace buffer with TIM-P and invalid
message detection.
•
Computes and compare B3, REI-L and REI-P
errors.
•
Computes and compare BIP-8 (B1, B2) and counts
the errors.
•
Performs ATM cells and PPP packets data extrac-
tion.
POS
•
Provides 8/16-bit extended POS Level 2 compliant
system interface with flag sequence detection/
insertion and CRC-CCITT/CRC-32 FCS genera-
tion/validation.
•
Maps POS packets into/from SONET SPE accord-
ing to RFC 2615 and 1662 of the IETF.
•
Supports packet based link protocols by using byte
synchronous HDLC framing like PPP HDLC and
,
frame relay.
•
Performs transmit HDLC frame insertion and
receive data extraction.
•
Performs self-synchronous data scrambling and de-
scrambling using 1+X43 polynomial.
•
Performs transmit flag sequence insertion and
receive synchronization.
•
Performs byte stuffing and de-stuffing for transpar-
ency processing.
•
Supports optional flow-through mode.
•
Performs abort sequence abortion and detection.
•
Arbitrary packet length (1 or more octets) and flag
sharing (single flag between frames).
•
Provide minimum and maximum packet length
checking, removing and reporting.
•
Transparency by octet stuffing of flag (0x7E), con-
trol escape (0x7D) and abort sequence.
•
Automatic transfer halt on receive FIFO host-side at
end of packet.
•
Error detection for Underflow of transmit FIFO,
Overflow of receive FIFO, parity error on transmit.
•
Optional removal of FCS from receive frames.
•
Optional transmit FCS insertion.
ATM
•
Provides a UTOPIA Level-2 compliant system inter-
face with cell payload scrambling and descram-
bling.
•
Maps ATM packets into/from SONET SPE accord-
ing to ATM Forum User Network Interface Specifi-
cation.
•
Implements the ATM physical layer for Broadband
ISDN according to ITU-T Recommendation I.432.
•
Provides selectable on-going HEC insertion and
verification.
•
Provides selectable COSET addition and removal.
•
Provides single bit error correction and multiple bit
error detection for HEC processing.
•
Provides HEC correctable and uncorrectable indi-
cations.
•
Supports external cell GFC insertion and extrac-
tion.
•
Provides the functions of cell rate de-coupling; idle
cell insertion and deletion, 16-cell FIFO cell buffer-
ing, programmable idle cell header and payload
and idle cell HEC generation.
•
Offers cell delineation with three states (hunt, pre-
sync, and sync) synchronization algorithm and pro-
vides LCD (Loss of Cell Delineation) indication and
interrupt.
•
Supports multiple programmable VPI/VCI filters.
•
Provides self-synchronizing SDH cell scrambling/
de-scrambling.
•
Supports OAM cell insertion and extraction with
dedicated cell store via microprocessor interface.
Transmission is enabled through semaphore.
•
Provides TxCell and TxCell indication signals.
•
Provides test cell generation and verification.
AUTOMATIC PROTECTION SWITCHING (APS)
•
Four OC-3 ports can be paired as two 1+1 pro-
tected OC-3 interfaces.
•
Four OC-3 ports can be configured as 1:1, 1:2 or
1:3 protected OC-3 interfaces.
•
Multiple 94L34's can be connected to provide up to
1:14 protected OC-3 interfaces.
•
APS functions facilitated via a bi-directional APS
interface and the transmit bridge and receive switch
blocks consisting of 5 to 5 cross connects.
2
áç
PRELIMINARY
XRT95L34
OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S
REV. P1.0.1
HIGH SPEED INTERFACE
•
Quad serial OC-3/STM-1 PECL interfaces with inte-
grated CDR, compatible with industry standard
optical modules.
•
Single serial OC-12/STM-4 PECL interface with
integrated CDR, compatible with industry standard
optical modules.
LOW SPEED INTERFACE
•
Complies with ATM forum Utopia Level 2/3 Specifi-
cation
•
Supports 8/16-bit 75MHz transmit and receive
interface.
•
Provides up to total 16 cell buffers for transmit and
receive.
•
Transmits and receives both 52 and 54 byte cell.
•
Generates and checks data parity of Utopia inter-
face.
•
Supports programmable Transmit Clav (transmit
cell available) signal for 0, 1, 2, 3 cell look ahead.
•
Supports programmable Receive Clav (receive cell
available) signal for 0, 1, 2, 3 byte look ahead.
•
Multiple POS transmit and receive streams.
•
Direct and polled port FIFO status indication in
transmit and receive direction.
•
Utopia level 2/3 (75 MHz maximum)-style status
reporting and flow control in chunk mode.
•
Independent addressing of transmit and receive
streams.
•
In-band port identification of receive ports.
•
Out-of-band or in-band transmit port selection.
•
Chunk (fixed maximum size) data transfer at full
rate in both transmit and receive direction.
•
Chunk size selectable in power-of-2 sizes (4 octets
to 128 octets).
•
Optional 2-cycle pause at end of packet in packet
mode.
•
Cycle-by-cycle data transfer flow control by link
layer.
•
Selectable port base addresses.
•
Provides 8/16-bit up to 50 MHz industrial standard
POS Level 2 interface.
SECTION, LINE, STS-PATH OVERHEAD INTER-
FACE
•
Provides serial access to all Section, Line and STS
Path Overhead data for 4xOC-3 and 1xOC-12 inter-
faces.
•
Provides serial access to DCC channels for direct
connection to standard HDLC processors.
MICROPROCESSOR INTERFACE
•
Supports standard 8-bit micro-controllers with Intel
or Motorola style interfaces.
•
·33 MHz read and write access.
•
Provides burst bus transfers.
•
Separated and multiplexed data/address bus.
•
Both write-clear and reset-upon-read for control of
status registers.
•
Provides interrupts for alarm processing.
PERFORMANCE MONITORING
•
Supports line and path performance monitoring.
•
Provides 32-bit saturating counter of idle cells
transmitted.
•
Provides 32-bit saturating counter of assigned cells
transmitted.
•
Provides 32-bit saturating counter of valid cells
received.
•
Provides 32-bit saturating counter of idle cells
received.
•
Provides 32-bit saturating counter of cells received
with HEC error.
•
Provides 32-bit saturating counter of cell discarded.
•
Provides 32-bit saturating counter of OOF errors.
•
Provides 32-bit saturating counter of LOF errors.
•
Provides 32-bit saturating counter of LOS errors.
•
Provides 32-bit saturating counter of SD errors.
•
Provides 32-bit saturating counter of SF errors.
•
Provides 32-bit saturating counter of B3 errors.
•
Provides 32-bit saturating counter of line RDI.
•
Provides 32-bit saturating counter of path AIS.
•
Provides 32-bit saturating counter of REI-L errors.
•
Provides 32-bit saturating counter of REI-P errors.
•
Provides 32-bit saturating counter of BIP-8 (B1,B2),
B3 errors.
•
Provides 32-bit saturating counter of loss of pointer.
•
Provides 32-bit saturating counter of POS frame
check sequence errors.
•
Provides 32-bit saturating PPP good frame counter.
•
Provides 32-bit saturating PPP Bad FCS counter.
•
Provides 32-bit saturating PPP aborted frame
counter.
•
Provides 32-bit saturating PPP Runt frame counter.
3
XRT95L34
OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S
REV. P1.0.1
áç
PRELIMINARY
INTERRUPT, STATUS AND TEST
•
Provides individually maskable interrupts.
•
Provides one second interrupt generations.
•
Generates interrupts from the following causes:
LOS status change, SONET OOF status change,
COFA, Utopia/PPP parity error, Utopia/PPP FIFO
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT95L34
overrun, Utopia/PPP FIFO under-run, Change of
cell alignment, HEC errors, LCD status change.
•
Provides local and remote line loopback.
•
Provides SONET remote loopback.
ATM
POS
STS-12
Section/
Line
Overhead
Processor
OC-12
Line
OC-12
CDR
ATM
POS
Pointer
Processor
Path
Overhead
APS
Switch
POS
Level 2
or
UTOPIA
Level 2
OC-3
Line
OC-3
Line
OC-3
Line
OC-3
Line
4
X
OC-3
CDR
4xSTS-3
Section/
Line
Overhead
Processor
ATM
POS
POS Level 2
or
Utopia Level 2
Interface
ATM
POS
Overhead Add/Drop Bus
APS
Port
Microprocessor Interface
JTAG Test
Port
XRT95L34
ORDERING INFORMATION
P
ART
N
UMBER
XRT95L34IV
P
ACKAGE
584 Ball TBGA
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
4
áç
PRELIMINARY
XRT95L34
OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S
REV. P1.0.1
XRT95L34 POS/ATM APPLICATIONS
F
IGURE
2. M
ULTI
-
PROTOCOL
R
OUTER
A
PPLICATION
O C -12 Line
95L34
or
O C -1 2
4 x O C -3
P O S /A T M
F ra m e r
P O S L evel 2/
U top ia L evel 2
N etwork
P rocessor
S w itch
Fabric
O C -3 L in e
O C -3 L in e
O C -3 L in e
O C -3 L in e
F
IGURE
3. OC-12 C
ONCENTRATOR
A
PPLICATION
DS3/E3
Mapper
8
19 MHz
8
19 MHz
DS3/E3
Mapper
DS3/E3
LIU
95L34
OC-12
Line
OC-12
4xOC-3
POS/ATM
Framer
DS3/E3
LIU
8
19 MHz
DS3/E3
Mapper
HDLC
Controller
8
19 MHz
DS3/E3
Mapper
HDLC
Controller
5
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