HD74AC283/HD74ACT283
4-bit Binary Full Adder with Fast Carry
ADE-205-388 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC283/HD74ACT283 high-speed 4-bit binary full adder with internal carry lookahead accepts
two 4-bit binary works (A
0
– A
3
, B
0
– B
3
) and a Carry input (C
0
). It generates the binary Sum outputs (S
0
–
S
3
) and the Carry output (C
4
) from the most significant bit. The HD74AC283/HD74ACT283 will operate
with either active High or active Low operands (positive or negative logic).
Features
•
Outputs Source/Sink 24 mA
•
HD74ACT283 has TTL-Cmpatible Inputs
Pin Arrangement
S
1
1
B
1
2
A
1
3
S
0
4
A
0
5
B
0
6
C
0
7
GND 8
(Top view)
16 V
CC
15 B
2
14 A
2
13 S
2
12 A
3
11 B
3
10 S
3
9 C
4
HD74AC283/HD74ACT283
Logic Symbol
A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
C
0
C
4
S
0
S
1
S
2
S
3
Pin Names
A
0
– A
3
B
0
– B
3
C
0
S
0
– S
3
C
4
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
Functional Description
The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C
0
).
The binary sum appears on the Sum (S
0
– S
3
) and outgoing carry (C
4
) outputs. The binary weight of the
various inputs and outputs is indicated by the subscript numbers, representing powers of two.
2
0
(A
0
+ B
0
+ C
0
) + 2
1
(A
1
+ B
1
) + 2
2
(A
2
+ B
2
) + 2
3
(A
3
+ B
3
) = S
0
+ 2S
1
+ 4S
2
+ 8S
3
+ 16C
4
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation. Thus C
0
, A
0
, B
0
can be arbitrarily
assigned to pins 5, 6 and 7 for DIPS. Due to the symmetry of the binary add function, the
HD74AC283/HD74ACT283 can be used either with all inputs and outputs active High (positive logic) or
with all inputs and outputs active Low (negative logic). See Figure a. Note that if C
0
is not used it must be
tied Low for active High logic or tied High for active Low logic.
Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for
use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a
carry out from, an intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs
of the fourth adder (A
3
, B
3
) Low makes S
3
dependent only on, and equal to, the carry from the third adder.
Using somewhat the same principle Figure c shows a way of dividing the HD74AC283/HD74ACT283 into
a 2-bit and a 1-bit adder. The third stage adder (A
2
, B
2
, S
2
) is used merely as a means of getting a carry
(C
10
) signal into the fourth stage (via A
2
and B
2
) and bringing out the carry from the second stage on S
2
.
Note that as long as A
2
and B
2
are the same, whether High or Low, they do not influence S
2
. Similarly,
when A
2
and B
2
are the same the carry into the third stage does not influence the carry out of the third
2
HD74AC283/HD74ACT283
stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted.
The outputs S
0
, S
1
and S
2
present a binary number equal to the number of inputs I
1
– I
5
that are true. Figure
e shows one method of implementing a 5-input majority gate. When three or more of the inputs I
1
– I
5
are
true, the output M
5
is true.
Fig. a Active HIGH varsus Active LOW Interpretation
C
0
Logic levels
Active HIGH
Active LOW
L
0
1
A
0
L
0
1
A
1
H
1
0
A
2
L
0
1
A
3
H
1
0
B
0
H
1
0
B
1
L
0
1
B
2
L
0
1
B
3
H
1
0
S
0
H
1
0
S
1
H
1
0
S
2
L
0
1
S
3
L
0
1
C
4
H
1
0
Active HIGH: 0 + 10 + 9 = 3 + 16
Active LOW: 1 + 5 + 6 = 12 + 0
L
A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
C
0
C
4
S
0
S
1
S
2
S
3
C
3
Fig. b 3-bit Adder
C
10
A
0
B
0
A
1
B
1
A
10
B
10
A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
C
4
C
11
C
0
C
0
S
0
S
1
S
2
S
3
S
0
S
1
C
2
S
10
Fig. c 2-bit and 1-bit adders
3
HD74AC283/HD74ACT283
Logic Diagram
C
0
A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
S
0
S
1
S
2
S
3
C
4
Please note that this diagram is provided only for the understanding of logic operations and shoudl not be
used to estimate propagation delays.
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Maximum I
CC
/input (HD74ACT283)
Symbol
I
CC
I
CC
I
CCT
Max
80
8.0
1.5
Unit
µA
µA
mA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
V
IN
= V
CC
– 2.1 V, V
CC
= 5.5 V,
Ta = Worst case
5
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