®
ISL8700, ISL8701, ISL8702, ISL8702A,
ISL8703, ISL8704, ISL8705
Data Sheet
March 14, 2006
FN9250.0
Adjustable Quad Sequencer
The ISL8700, ISL8701, ISL8702, ISL8702A, ISL8703,
ISL8704, ISL8705 family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
High performance DSP, FPGA, µP and various subsystems
require input power sequencing for proper functionality at
initial power up and the ISL870X provides this function while
monitoring the distributed voltage for over and undervoltage
compliance.
The ISL8700 and ISL8701 operate over the +2.5V to +24V
nominal voltage range, whereas the ISL8702 operates over
the 2.5V to +12V range. All three have a user adjustable
time from UV and OV voltage compliance to sequencing
start via an external capacitor when in auto start mode and
adjustable time delay to subsequent ENABLE output signal
via external resistors.
Additionally, ISL8702A, ISL8703, ISL8704 and ISL8705
provide I/O for sequencing on and off operation (SEQ_EN)
and for voltage window compliance reporting (FAULT) over
the +2.5V to +24V voltage range. The ISL8702 also has this
feature but operates over the 2.5V to +12V range.
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870X provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
Features
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
• Under and Overvoltage Adjustable Delay to Auto Start
Sequence
• I/O Options
ENABLE (ISL8700, ISL8702, ISL8702A, ISL8704) and
ENABLE# (ISL8701, ISL8703, ISL8705)
SEQ_EN (ISL8702, ISL8702A, ISL8703) and SEQ_EN#
(ISL8704, ISL8705)
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing
• System Timing Function
Pinout
ISL870X
(14 LD SOIC)
TOP VIEW
ENABLE_D 1
ENABLE_C 2
ENABLE_B 3
ENABLE_A 4
OV 5
UV 6
GND 7
14 VIN
13 TD
12 TC
11 TB
10 TIME
9 SEQ_EN (NC on ISL8700/01)
8 FAULT (NC on ISL8700/01)
Ordering Information
PART NUMBER
(Notes 1, 2)
ISL8700IBZ*
ISL8701IBZ*
ISL8702IBZ*
ISL8702AIBZ-T
ISL8703IBZ*
ISL8704IBZ*
ISL8705IBZ*
ISL8703IBZ
ISL8704IBZ
ISL8705IBZ
PART
MARKING
ISL8700IBZ
ISL8701IBZ
ISL8702IBZ
TEMP.
RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
PKG.
DWG. #
M14.15
M14.15
M14.15
ISL8701, ISL8703, ISL8705 PINS 1-4 ARE ENABLE# FUNCTION
ISL8704, ISL8705 PIN 9 IS SEQ_EN# FUNCTION
14 Ld SOIC
M14.15
(Tape and Reel)
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
M14.15
M14.15
M14.15
2.5-24V (12Vmax for ISL8702)
EN
DC/DC
ENABLE_A
ENABLE_B
ENABLE_C
ENABLE_D
FAULT *
Ru
VIN
SEQ_EN *
UV
Vo1
ISL870XEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel.
NOTES:
1. Part Numbers in
Bold
are available now, others will soon be available,
contact factory for availability schedule.
2. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Rl
Rm
EN
DC/DC
Vo2
OV
GND TB TC TD TIME
EN
DC/DC
Vo3
EN
DC/DC
V04
* SEQ_EN and FAULT are not available on ISL8700 and ISL8701
FIGURE 1. ISL870X IMPLEMENTATION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Absolute Maximum Ratings
V
IN
, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V
ISL8702 V
IN
, ENABLE(#), FAULT . . . . . . . . . . . . . . . . 14V, to -0.3V
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN
+0.3V, to -0.3V
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical, Note 3)
θ
JA
(°C/W)
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 2.5V to 24V
ISL8702 Supply Voltage Range (Nominal) . . . . . . . . . . 2.5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
UV AND OV INPUTS
UV/OV Rising Threshold
UV/OV Falling Threshold
UV/OV Hysteresis
UV/OV Input Current
Nominal V
IN
= 2.5V to +24V, T
A
= T
J
= -40°C - 85°C, Unless Otherwise Specified.
ISL8702 V
IN
= 2.5V to +12V
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
UVRvth
V
UVFvth
V
UVhys
I
UV
V
UVRvth
- V
UVFvth
1.16
1.06
-
-
1.21
1.10
104
10
1.28
1.18
-
-
V
V
mV
nA
TIME, ENABLE/ENABLE# OUTPUTS
TIME Pin Charging Current
TIME Pin Threshold
Time from V
IN
Valid to ENABLE_A
I
TIME
V
TIME_VTH
t
VINSEQpd
t
VINSEQpd_10
t
VINSEQpd500
Time from V
IN
Invalid to Shutdown
ENABLE Output Resistance
ENABLE Output Low
ENABLE Pull-down Current
Delay to Subsequent ENABLE Turn-on/off
t
shutdown
R
EN
Vol
I
pulld
t
del_120
t
del_3
t
del_0
SEQUENCE ENABLE AND FAULT I/O
V
IN
Valid to FAULT Low
V
IN
Invalid to FAULT High
FAULT Pull-down Current
SEQ_EN Pull-up Voltage
SEQ_EN Low Threshold Voltage
SEQ_EN High Threshold Voltage
Delay to ENABLE_A Deasserted
V
SEQ
Vil
SEQ_EN
Vih
SEQ_EN
t
SEQ_EN_ENA
SEQ_EN low to ENABLE_A low
t
FLTL
t
FLTH
FAULT = 1V
SEQ_EN open
15
-
10
-
-
1.2
-
30
0.5
15
V
IN
-
-
0.2
50
-
-
-
0.3
-
1
µs
µs
mA
V
V
V
µs
SEQ_EN = high, C
TIME
= open
SEQ_EN = high, C
TIME
= 10nF
SEQ_EN = high, C
TIME
= 500nF
UV or OV to simultaneous shutdown
I
ENABLE
= 1mA
I
ENABLE
= 1mA
ENABLE = 1V
R
TX
= 120kΩ
R
TX
= 3kΩ
R
TX
= 0Ω
-
1.9
-
-
-
-
-
-
10
155
3.5
-
2.6
2.0
30
7.7
435
-
100
0.1
15
195
4.7
0.5
-
2.25
-
-
-
1
-
-
-
240
6
-
µA
V
µs
ms
ms
µs
Ω
V
mA
ms
ms
ms
2
FN9250.0
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Electrical Specifications
PARAMETER
BIAS
IC Supply Current
I
VIN_2.2V
I
VIN_12V
I
VIN_24V
V
IN
Power On Reset
V
IN_POR
V
IN
= 2.2V
V
IN
= 12V
V
IN
= 24V
V
IN
low to high
-
-
-
-
191
246
286
2.08
-
400
-
2.5
µA
µA
µA
V
Nominal V
IN
= 2.5V to +24V, T
A
= T
J
= -40°C - 85°C, Unless Otherwise Specified.
ISL8702 V
IN
= 2.5V to +12V
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pin Descriptions
PINS
870
0
NA
1
NA
2
NA
3
NA
4
5
870
1
1
NA
2
NA
3
NA
4
NA
5
8702
8702A
NA
1
NA
2
NA
3
NA
4
5
870
3
1
NA
2
NA
3
NA
4
NA
5
870
4
NA
1
NA
2
NA
3
NA
4
5
870
5
1
NA
2
NA
3
NA
4
NA
5
PIN NAME
ENABLE#_
D
ENABLE_D
ENABLE#_
C
ENABLE_C
FUNCTION DESCRIPTION
Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701, ISL8703, ISL8705. Tracks V
IN
upon bias.
Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to
sequence off for the ISL8700, ISL8702, ISL8704. Pulls low with V
IN
< 1V.
Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701, ISL8703, ISL8705. Tracks V
IN
upon bias.
Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700, ISL8702, ISL8704. Pulls low with V
IN
< 1V.
ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701, ISL8703, ISL8705. Tracks V
IN
upon bias.
ENABLE_B
Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700, ISL8702, ISL8704. Pulls low with V
IN
< 1V.
ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701, ISL8703, ISL8705. Tracks V
IN
upon bias.
ENABLE_A
OV
Active high open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE_B for the ISL8700, ISL8702, ISL8704. Pulls low with V
IN
< 1V.
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull ups.
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull ups.
IC ground.
The V
IN
voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than V
IN
via an external resistor.
This pin provides a sequence on signal input with a high input. Internally pulled high to V
IN
.
This pin provides a sequence on signal input with a low input. Internally pulled high to V
IN
.
This pin provides a 2.6µA current output so that an adjustable V
IN
valid to sequencing on and
off start delay period is created with a capacitor to ground.
A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
IC Bias Pin Nominally 2.5V to 24V
(12V max for ISL8702).
This pin requires a 1µF decoupling capacitor close to IC pin.
6
6
6
6
6
6
UV
7
NA
NA
NA
10
11
7
NA
NA
NA
10
11
7
8
9
NA
10
11
7
8
9
NA
10
11
7
8
NA
9
10
11
7
8
NA
9
10
11
GND
FAULT
SEQ_EN
SEQ_EN#
TIME
TB
12
12
12
12
12
12
TC
13
13
13
13
13
13
TD
14
14
14
14
14
14
V
IN
3
FN9250.0
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Functional Block Diagram
VIN (2.2V MIN - 27V MAX, 14V for ISL8702)
VIN
VREF
1.17V
VOLTAGE
REFERENCE
VIN INTERNAL VOLTAGE
3.5V
REGULATOR
SEQ_EN
UV
+
-
+
OV
FAULT
30µs
GND
-
eo
LOGIC
2.0V VIN POR
ENABLE_A
ENABLE_B
ENABLE_C
V
TIME_VTH
VIN
2.6µA
PROGRAMMABLE
DELAY TIMER
ENABLE_D
TIME
TB
TC
TD
Functional Description
The ISL870X family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 2.5V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870X initiate the pre-programmed A-B-C-D sequence of the
ENABLE (ISL8700, ISL8702, ISL8704) or ENABLE# (ISL8701,
ISL8703, ISL8705) outputs. Although this IC has a bias range
of 2.5V to 24V (12V for ISL8702) it can monitor any voltage
>1.22V via the external divider if a suitable bias voltage is
otherwise provided.
During initial bias voltage (V
IN
) application the ISL8700,
ISL8702, ISL8704 ENABLE outputs are held low once
V
IN
= 1V whereas the ISL8701, ISL8703, ISL8705 ENABLE#
outputs follow the rising V
IN
. Once V
IN
> the V bias power on
reset threshold (POR) of 2.0V, V
IN
is constantly monitored for
compliance via the input voltage resistor divider and the
voltages on the UV and OV pins and reported by the FAULT
output. Internally, voltage regulators generate 3.5V and 1.17V
±5% voltage rails for internal usage once V
IN
> POR. Once UV
> 1.22V and with the SEQ_EN pin high or open, (SEQ_EN#
must be pulled low on ISL8704, ISL8705) the auto sequence of
the four ENABLE (ENABLE#) outputs begins as the TIME pin
charges its external capacitor with a 2.6µA current source. The
voltage on TIME is compared to the internal reference
(V
TIME_VTH
) comparator input and when greater than
V
TIME_VTH
the ISL8700, ISL8702, ISL8704 ENABLE_A is
released to go high via an external pull-up resistor or a pull-up
in a DC/DC convertor enable input, for example. Conversely,
ENABLE#_A output will be pulled low at this time on an
ISL8701, ISL8703, ISL8705. The time delay generated by the
external capacitor is to assure continued voltage compliance
within the programmed limits, as during this time any OV or UV
condition will halt the start-up process. TIME cap is discharged
once V
TIME_VTH
is met.
Once ENABLE_A is active (either released high on the
ISL8700, ISL8702, ISL8704 or pulled low, ISL8701, ISL8703,
ISL8705) a counter is started and using the resistor on TB as a
timing component a delay is generated before ENABLE_B is
activated. At this time, the counter is restarted using the resistor
on TC as its timing component for a separate timed delay until
ENABLE_C is activated. This process is repeated for the
resistor on TD to complete the A-B-C-D sequencing order of
the ENABLE or ENABLE# outputs. At any time during
sequencing if an OV or UV event is registered, all four ENABLE
outputs will immediately return to their reset state; low for
ISL8700, ISL8702, ISL8704 and high for ISL8701, ISL8703,
ISL8705. C
TIME
is immediately discharged after initial ramp up
thus waiting for subsequent voltage compliance to restart. Once
FN9250.0
March 14, 2006
4
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
sequencing is complete, any subsequently registered UV or OV
event will trigger an immediate and simultaneous reset of all
ENABLE or ENABLE# outputs.
On the ISL8702, ISL8703, ISL8704 and ISL8705, enabling of
on or off sequencing can also be signaled via the SEQ_EN or
SEQ_EN# input pin once voltage compliance is met. Initially the
SEQ_EN pin should be held low and released when sequence
start is desired. The SEQ# is internally pulled high and
sequencing is enabled when it is pulled low. The on sequence
of the ENABLE outputs is as previously described. The off
sequence feature is only available on the variants having the
SEQ_EN or the SEQ_EN# inputs, these being the ISL8702,
ISL8703, ISL8704, ISL8705. The sequence is D off, then C off,
then B off and finally A off. Once SEQ_EN (SEQ_EN#) is
signaled low (high) the TIME cap is charged to 2V once again.
Once this Vth is reached ENABLE_D transitions to its reset
state and CTIM is discharged. A delay and subsequent
sequence off is then determined by TD resistor to ENABLE_C.
Likewise, a delay to ENABLE_B and then ENABLE_A turn-off
is determined by TC and TB resistor values respectively.
With the ISL8700, ISL8701 a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The following is a practical example worked out. For detailed
equatons on how to perform this operation for a given supply
requirement please see the next section.
1. Determine if turn-on or shutdown limits are preferred and
in this example we will determine the resistor values
based on the shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, Ir = divider
current
4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
5. Rm+Rl = 1.1V/Ir @ UV
=
Rm+Rl = 1.1V/(10.8V/100kΩ) =
10.370kΩ
6. Rl = 1.2V/Ir @ OV
=
Rl = 1.2V/(13.2V/100kΩ) = 9.242k
Ω
7. Rm = 10.370kΩ - 9.242kΩ = 1.128kΩ
8. Ru = 100kΩ - 10.370kΩ = 89.630kΩ
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors.values.
In our example with the closest standard values of
Ru = 90.9kΩ, Rm = 1.13kΩ and Rl = 9.31kΩ, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
Programming the Under and Overvoltage Limits
When choosing resistors for the divider remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ -1000kΩ range is advisable
with high precision resistors being used to reduce monitoring
error. Although for the ISL870X two dividers of two resistors
each can be employed to separately monitor the OV and UV
levels for the V
IN
voltage we will discuss here using a single
three resistor string for monitoring the V
IN
voltage, referencing
Figure 1. In the three resistor divider string with Ru (upper), Rm
(middle) & Rl (lower) the ratios of each in combination to the
other two is balanced to achieve the desired UV & OV trip
levels. Although this IC has a bias range of 2.5V to 24V (12V for
ISL8702) it can monitor any voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (gnd connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
5
FN9250.0
March 14, 2006
Analogue and Mixed Signal
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