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DPS512X8MKN3-25B

Description
SRAM Module, 512KX8, 25ns, CMOS, STACK, DIP-32
Categorystorage    storage   
File Size485KB,6 Pages
ManufacturerTwilight Technology Inc.
Download Datasheet Parametric View All

DPS512X8MKN3-25B Overview

SRAM Module, 512KX8, 25ns, CMOS, STACK, DIP-32

DPS512X8MKN3-25B Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerTwilight Technology Inc.
Parts packaging codeMODULE
package instructionDIP, DIP32,.6
Contacts32
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Is SamacsysN
Maximum access time25 ns
I/O typeCOMMON
JESD-30 codeR-XDMA-T32
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX8
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum standby current0.0018 A
Minimum standby current2 V
Maximum slew rate0.18 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
512Kx8, 20 - 45ns, STACK/DIP
30A129-11
D
4 Megabit High Speed CMOS SRAM
DPS512X8MKN3
PRELIMINARY
DESCRIPTION:
The DPS512X8MKN3 High Speed SRAM ‘’STACK’’
devices are a revolutionary new memory subsystem
using Dense-Pac Microsystems’ ceramic Stackable
Leadless Chip Carriers (SLCC) mounted on a co-fired
ceramic substrate having side-brazed leads.
The
device packs 4-Megabits of low-power CMOS static
RAM in a 600-mil-wide, 32-pin dual-in-line package
that conforms to the same JEDEC standard pin
configuration.
The DPS512X8MKN3 STACK devices contain an
individual 512K x 8 SRAM die, packaged in a
hermetically sealed SLCC, making the devices suitable
for commercial, industrial and military applications.
By using SLCCs, the ‘’Stack’’ family of devices offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
Organizations Available:
Access Times:
20, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
Package Available: 32 Pin DIP
2.0V min.
PIN-OUT DIAGRAM
512K x 8
PIN NAMES
A0 - A18
I/O0 - I/O7
CE
WE
OE
V
DD
V
SS
Address Inputs
Data Input/Output
Low Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
30A129-11
REV. D
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
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