512Kx8, 20 - 45ns, STACK/DIP
30A129-11
D
4 Megabit High Speed CMOS SRAM
DPS512X8MKN3
PRELIMINARY
DESCRIPTION:
The DPS512X8MKN3 High Speed SRAM ‘’STACK’’
devices are a revolutionary new memory subsystem
using Dense-Pac Microsystems’ ceramic Stackable
Leadless Chip Carriers (SLCC) mounted on a co-fired
ceramic substrate having side-brazed leads.
The
device packs 4-Megabits of low-power CMOS static
RAM in a 600-mil-wide, 32-pin dual-in-line package
that conforms to the same JEDEC standard pin
configuration.
The DPS512X8MKN3 STACK devices contain an
individual 512K x 8 SRAM die, packaged in a
hermetically sealed SLCC, making the devices suitable
for commercial, industrial and military applications.
By using SLCCs, the ‘’Stack’’ family of devices offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
•
Organizations Available:
•
Access Times:
20, 25, 30, 35, 45ns
•
Fully Static Operation
- No clock or refresh required
•
Single +5V Power Supply,
±
10% Tolerance
•
TTL Compatible
•
Common Data Inputs and Outputs
•
Low Data Retention Voltage:
•
Package Available: 32 Pin DIP
2.0V min.
PIN-OUT DIAGRAM
512K x 8
PIN NAMES
A0 - A18
I/O0 - I/O7
CE
WE
OE
V
DD
V
SS
Address Inputs
Data Input/Output
Low Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
30A129-11
REV. D
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS512X8MKN3
PRELIMINARY
TRUTH TABLE
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
Supply
I/O Pin Current
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
3
3
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
Symbol
Characteristic
V
DD
Supply Voltage
V
IH
Input HIGH Voltage
V
IL
Input LOW Voltage
M/B
Operating
T
A
I
Temperature
C
Min.
4.5
2.2
-0.5
2
-55
-40
0
Max. Unit
5.5
V
V
DD
+0.3 V
0.8
V
+25 +125
o
+25
+85
C
+25
+70
Typ.
5.0
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Value
Storage Temperature
-65 to +150
Temperature Under Bias
-55 to +125
1
Supply Voltage
-0.5 to +7.0
Input/Output Voltage
1
-0.5 to V
DD
+0.5
Unit
°C
°C
°C
V
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
CAPACITANCE
4
: T
A
= 25
°
C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
10
10
10
10
12
Unit
Condition
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
pF
V
IN2
= 0V
Figure 1. Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4
V
D
OUT
C
L
*
255Ω
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3.0V)
Data Retention
Supply Current (2.0V)
Output Low Voltage
Output High Voltage
o
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V
I
OUT
= 8.0mA
I
OUT
= -4.0mA
Typ.
(†)
-
-
125
1
20
150
100
-
-
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
µA
µA
mA
mA
mA
µA
µA
V
V
-5
-10
+5
+10
170
10
60
500
300
0.4
-5
-10
+5
+10
180
10
60
1000
800
0.4
-5
-10
+5
+10
180
15
60
2000
1800
0.4
2.4
2.4
2.4
† Typical measurements made at +25 C, Cycle = min., V
DD
= 5.0V.
2
30A129-11
REV. D
Dense-Pac Microsystems, Inc.
DPS512X8MKN3
PRELIMINARY
Data Retention AC Characteristics
8
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
10
3
0
0
4
8
8
25
25
25
12
3
0
0
5
10
10
30
30
30
15
3
0
0
5
15
15
35
35
35
20
3
0
0
5
20
20
45
45
45
25
3
0
0
5
25
25
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time *
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
13
13
0
13
0
0
9
0
3
8
25
15
15
0
15
0
0
10
0
3
10
30
20
20
0
20
0
0
12
0
3
12
35
25
25
0
25
0
0
15
0
3
15
45
35
35
0
35
0
0
20
0
3
20
* Valid for both Read and Write Cycles.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
30A129-11
REV. D
CE
≥
V
DD
-0.2V
3
DPS512X8MKN3
PRELIMINARY
READ CYCLE
ADDRESS
Dense-Pac Microsystems, Inc.
CE
OE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
4
30A129-11
REV. D
Dense-Pac Microsystems, Inc.
DPS512X8MKN3
PRELIMINARY
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A129-11
REV. D
5
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