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MPC8541EPXAJD

Description
32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
Categorysemiconductor    The embedded processor and controller   
File Size1MB,84 Pages
ManufacturerFREESCALE (NXP)
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MPC8541EPXAJD Overview

32-BIT, 533 MHz, RISC PROCESSOR, PBGA783

MPC8541EPXAJD Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals783
Maximum operating temperature105 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage1.26 V
Minimum supply/operating voltage1.14 V
Rated supply voltage1.2 V
External data bus width64
Line speed533 MHz
Processing package description29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeGRID ARRAY, HEAT SINK/SLUG
surface mountYes
Terminal formBALL
Terminal spacing1 mm
terminal coatingTIN LEAD
Terminal locationBOTTOM
Packaging MaterialsPLASTIC/EPOXY
Temperature levelOTHER
Address bus width64
Number of digits32
boundary scanYes
Maximum FCLK clock frequency166 MHz
floating point unitYes
Integrated cacheYes
low power modeYes
Microprocessor typeRISC PROCESSOR
Freescale Semiconductor
Technical Data
MPC8541EEC
Rev. 4, 12/2006
MPC8541E PowerQUICC™ III
Integrated Communications Processor
Hardware Specifications
The MPC8541E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8541E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the
MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ethernet: Three-Speed, MII Management . . . . . . . . . . 20
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 53
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
System Design Information . . . . . . . . . . . . . . . . . . . . . 75
Document Revision History . . . . . . . . . . . . . . . . . . . . 82
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 82
© Freescale Semiconductor, Inc., 2004, 2004, 2006. All rights reserved.
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